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检索条件"任意字段=5th Southern Conference on Programmable Logic"

共 390 条记录，以下是1-10 订阅

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Proceedings - 2009 5th southern conference on programmable logic, SPL 2009

Proceedings - 2009 5th Southern Conference on Programmable L...

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2009 5th southern conference on programmable logic, SPL 2009

ISBN: (纸本)9781424438464

the proceedings contain 38 papers. the topics discussed include: experiences applying OVM 2.0 to an 8B/I0B RTL design;T-NDPack: timing-driven non-uniform depopulation based clustering;PAM Map: an architecture-independent logic block mapping algorithm for SRAM-based FPGAs;automatic VHDL generation for solving rotation and scale invariant template matching in FPGA;a General image processing architecture for FPGA;FPGA/soft-processor based real-time object tracking system;hardware accelerated aerial image simulation by FPGA;SCBXP: an efficient hardware-based XML parsing technique;systolic array implementations for real time enhancement of remote sensing imaging;flexible communication support for dynamically reconfigurable FPGAs;and parameterized hardware design on reconfigurable computers: an image registration case study.

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Proceedings - 2009 5th southern conference on programmable logic, SPL 2009: Preface

Proceedings - 2009 5th Southern Conference on Programmable L...

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Proceedings - 2009 5th southern conference on programmable logic, SPL 2009 2009年 ii-iii页

作者： Carlos, São

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A Optimized Reversible Design for programmable Array logic Based on Quantum Computing Nanotechnology 5th

A Optimized Reversible Design for Programmable Array Logic B...

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5th International conference on Electrical and Electronics Engineering, ICEEE 2024

作者： Akter, Fatema Tabassum, Tamanna Md. Al Amin Meia Majumder, Pranab Khan, Noor Hasan Mahmud Department of Computer Science and Engineering Green University Bangladesh Purbachal Bangladesh Department of Computer Science and Engineering Jagannath University Dhaka Bangladesh Department of Mathematics Government Titumir College Dhaka Bangladesh Department of Mathematics Lamar University Beaumont United States Department of Business Administration European University of Bangladesh Dhaka Bangladesh

ISBN: (纸本)9789819790364

Using the ideas of quantum physics, quantum computing is a new technology that can solve issues that traditional computers are unable to. It utilizes quantum processes to develop novel forms of computation, with qubits as its fundamental units. the core concepts of quantum physics that underpin quantum computing are superposition and entanglement. these ideas enable quantum computers to perform jobs with orders of magnitude less energy consumption than traditional computers. In order to improve computing capabilities, this effort focuses on building Quantum logic Gates and programmable Array logic (PAL) employing Quantum Gates. Combinational and sequential logic circuits are created using programmable logic Devices (PALs). It is a flexible logic device that can be configured to carry out a variety of tasks, from simple logic gate operations to intricate system-on-chip layouts. Quantum-based PAL can do billions of operations concurrently thanks to the capabilities of quantum computing, significantly increasing computing power and efficiency. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： System-on-chip

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Towards Propositional KLM-Style Defeasible Standpoint logics 5th

Towards Propositional KLM-Style Defeasible Standpoint Logics

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5th southern African conference for Artificial Intelligence Research

作者： Leisegang, Nicholas Meyer, thomas Rudolph, Sebastian Univ Cape Town Cape Town South Africa CAIR Cape Town South Africa Tech Univ Dresden Dresden Germany Ctr Scalable Data Analyt & Artificial Intelligenc Dresden Germany

ISBN: (纸本)9783031782541;9783031782558

the KLM approach to defeasible reasoning introduces a weakened form of implication into classical logic. this allows one to incorporate exceptions to general rules into a logical system, and for old conclusions to be withdrawn upon learning new contradictory information. Standpoint logics are a group of logics, introduced to the field of Knowledge Representation in the last 5 years, which allow for multiple viewpoints to be integrated into the same ontology, even when certain viewpoints may hold contradicting beliefs. In this paper, we aim to integrate standpoints into KLM propositional logic in a restricted setting. We introduce the logical system of Defeasible Restricted Standpoint logic (DRSL) and define its syntax and semantics. Specifically, we integrate ranked interpretations and standpoint structures, which provide the semantics for propositional KLM and propositional standpoint logic respectively, in order to introduce ranked standpoint structures for DRSL. Moreover, we extend the non-monotonic entailment relation of rational closure from the propositional KLM case to the DRSL case. the main contribution of this paper is to characterize rational closure for DRSL both algorithmically and semantically, showing that rational closure can be characterized through a single representative ranked standpoint structure. Finally, we conclude that the semantic and algorithmic characterizations of rational closure are equivalent, and that entailment-checking for DRSL under rational closure is in the same complexity class as entailment-checking for propositional KLM.

关键词： Knowledge representation Non-monotonic reasoning Defeasible reasoning Standpoint logic

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Scalable Convolutional Neural Network Inference on-the-Edge using Low-Density FPGAs

Scalable Convolutional Neural Network Inference on-the-Edge ...

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Advanced Research in Computing (ICARC), International conference on

作者： Udara Ranabahu S A Suraweera Arachchige W A Susantha Wijesinghe School of Engineering Liverpool John Moores University Liverpool United Kingdom Faculty of Applied Sciences Wayamba University of Sri Lanka Kuliyapitiya Sri Lanka

ISBN: (数字)9798331530983

ISBN: (纸本)9798331530990

Machine learning (ML) inference-based applications are often considered to be computationally expensive and power exhaustive, restricting useful deployment in low-power use cases. To take advantage of ML in power-constrained edge environments, it is critical to reduce the power consumption and increase the overall efficiency, while aiming for performance *** present a characteristics study of a low-powered implementation of ML inference focused on-the-edge, aiming for increased efficiency and predictive cost estimation. A scalable inference accelerator architecture for Convolutional Neural Networks (CNNs) consisting of simple functional blocks was developed at Register-transfer Level (RTL) using Verilog® Hardware Description Language (HDL), and was verified at RTL-level verification using RTL testbenches. the integrated system went through functional verification against a predefined golden model, while being optimized for precision and logic *** accelerator was then converted into a fully-parameterized Reconfigurable FPGA IP with additional purpose-built custom debugging glue logic; and validated on FPGA hardware. the system showed a minimum of 740 times acceleration factor during recorded performance evaluations.

关键词： Maximum likelihood estimation Costs Hardware Silicon Convolutional neural networks IP networks logic Resource management Hardware design languages Field programmable gate arrays

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Research on Configuration Data Generation Algorithm for HyperParser

Research on Configuration Data Generation Algorithm for Hype...

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Power Electronics, Computer Applications (ICPECA), IEEE International conference on

作者： Peijun Ma Gongzhi Zhao Jiangyi Shi Cong Yao Weitao Pan Xidian University Xi'an China

ISBN: (数字)9798331533694

ISBN: (纸本)9798331533700

the evolution of technologies such as Big Data, Cloud Computing, and Artificial Intelligence is inextricably linked to the transmission of network data. programmable network devices that facilitate high-speed processing are becoming increasingly crucial. the significance of programmable parsers, as a constituent element of programmable network devices, is readily apparent. HyperParser has the advantages of low latency, high throughput, small area, low power consumption, and full programmability, but its configuration data generation algorithm is inefficient and has limited optimality. In this paper, the inefficiency in running speed is first optimized by subtree partitioning, and the preference for removing certain columns more conducive to approaching the global optimal solution is then analyzed from a probabilistic point of view. Using the big-union, edge network and enterprise network three kinds of parse graph test, the original algorithm in processing big-union in 10min failed to end the run, processing the rest of the two parse graphs consumed 0.1545s, 0.1513s, extracted the number of key bits 7 and 18; the algorithm proposed in this paper processing the three kinds of parse graphs consumed 3.679s, 0.019s and 0.019s, 3.679s, 0.019s and 0.027s, and the number of key bits extracted are 160, 7 and 17 respectively.

关键词： Cloud computing Power demand Computer applications Big Data throughput Probabilistic logic Power electronics Partitioning algorithms Low latency communication Optimization

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5th International Workshop on FPGAs for Software Programmers, FSP 2018, co-located with International conference on Field programmable logic and Applications, FPL 2018

5th International Workshop on FPGAs for Software Programmers...

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5th International Workshop on FPGAs for Software Programmers, FSP 2018, co-located with International conference on Field programmable logic and Applications, FPL 2018

ISBN: (纸本)9783800747238

the proceedings contain 9 papers. the topics discussed include: using Linux FIFOs to allow flexible hardware/software communications on reconfigurable systems-on-chip;improved parallelization of legacy embedded software on soft-core MPSoCs through automatic loop transformations;exact mapping of rewritten linear functions to configurable logic;ZUCL: a ZYNQ UltraScale+ framework for OpenCL HLS applications;unfolding and folding: a new approach for code restructuring targeting HLS for FPGAs;HatScheT: a contribution to agile HLS;LeFlow: enabling flexible fpga high-level synthesis of tensorflow deep neural networks;a case study in using OpenCL on FPGAs: creating an open-source accelerator of the AutoDock molecular docking software;and a journey into DSL design using generative programming: FPGA mapping of image border handling through refinement.

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Design of Network Environment Advertisable Multipath Transmission Control System for Mobile Device Support

Design of Network Environment Advertisable Multipath Transmi...

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Information Engineering (ACIE), IEEE Asia conference on

作者： Naoya Kitagawa Takehiko Kashiwagi Kohta Ohshima Research and Development Center for Academic Networks National Institute of Informatics Tokyo Japan The University of Electro-Communications Parallel Networks LLC. Tokyo Japan Marine Electromechanical Engineering Division Tokyo University of Marine Science and Technology Tokyo Japan

ISBN: (数字)9798331528409

ISBN: (纸本)9798331528416

Uninterrupted wireless communication on the move is important for remote drone/robot operation, self-driving cars, and maritime autonomous surface ships. this paper describes a functional extension design of our previously developed fieldprogrammable gate array (FPGA)-based multipath transmission control system. the new network environment advertisable method uses the Wi-Fi round-trip time (RTT) and low-power wide-area (LPWA) networks to address the issue of not knowing whether handover is possible until the device is in motion, because Wi-Fi AP scanning is limited to the wireless communication range. We show how to apply the method to the hardware that we previously developed and its practical applicability through performance evaluation of Wi-Fi RTT and LPWA communication.

关键词： Wireless communication Performance evaluation Handover logic gates Control systems Hardware Mobile handsets Marine vehicles Wireless fidelity Field programmable gate arrays

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PAM MAP: AN ARCHITECTURE-INDEPENDENT logic BLOCK MAPPING ALGORIthM FOR SRAM-BASED FPGAS

PAM MAP: AN ARCHITECTURE-INDEPENDENT LOGIC BLOCK MAPPING ALG...

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5th southern conference on programmable logic

作者： Shao, Yun Lai, Jinmei Wang, Jian Yong, Jiarong Fudan Univ ASIC Shanghai 201203 Peoples R China

ISBN: (纸本)9781424438464

In this paper, we consider the general problem of mapping a given logic circuit onto an SRAM-based FPGA with programmable logic blocks of arbitrary architectures. We formulate the problem as a graph matching problem and present an architecture-independent algorithm for this purpose. this algorithm also obtains a best area saving of 4% compared to architecture-dependent methods.

关键词： Computer circuits

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FLEXIBLE COMMUNICATION SUPPORT FOR DYNAMICALLY RECONFIGURABLE FPGAS

FLEXIBLE COMMUNICATION SUPPORT FOR DYNAMICALLY RECONFIGURABL...

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5th southern conference on programmable logic

作者： Devaux, Ludovic Chillet, Daniel Pillement, Sebastien Demigny, Didier Univ Rennes 1 IRISA F-22302 Lannion France

ISBN: (纸本)9781424438464

Dynamic reconfiguration of FPGAs allows the dynamic management of various tasks that describe an application. this new feature permits, for optimization purpose, to place tasks on line in an available region of the FPGA. Dynamic reconfiguration of tasks leads to some communication problems since tasks are not present in the matrix during all computation time. this dynamicity needs to be supported by the interconnection network. In this paper, we propose the implementation of a flexible interconnection network supporting such dynamicity. the proposed architecture is fully compliant with the present state-of-art. dynamically reconfigurable circuits such as Xilinx Virtex family of FPGA.

关键词： Field programmable gate arrays (FPGA)

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