A GPS/GLONASS clock synchronization implementation based on programmablelogic is presented. the GPS/GLONASS PPS (standard I second signal) is regarded as a reference of the whole clock synchronization system that con...
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ISBN:
(纸本)078037889X
A GPS/GLONASS clock synchronization implementation based on programmablelogic is presented. the GPS/GLONASS PPS (standard I second signal) is regarded as a reference of the whole clock synchronization system that consists of two levels PLL. Boththe GPS/GLONASS PPS and OCXO assure the long-term stability and short-term stability of clock signals. All the digital circuit. including digital phase error discriminator. 2S-generating module, phase error detecting and controlling module. can be built in a programmablelogic chip.
this paper describes a hardware implementation of aerial image simulation in lithography using FPGA. However, such simulators are presently performed using mainly softwarebased techniques on dedicated computers. the H...
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Bioinformatics applications are computationally very expensive programs. they work with large data sets and also consume a lot of CPU cycles and often require high degrees of precision. An important application in thi...
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Particle image velocimetry (PIV) allows measuring distributed flow velocity fields. It is well established as an experimental tool in modern fluid dynamics research, being applied to liquid, gases and multiphase flows...
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the extensive use of new programmablelogic devices as FPGAs in the design of digital systems has motivated a great interest in AND-EXOR logic. the advantages of this logic rest on boththe lower number of gates requi...
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the extensive use of new programmablelogic devices as FPGAs in the design of digital systems has motivated a great interest in AND-EXOR logic. the advantages of this logic rest on boththe lower number of gates required with respect to the usual AND-OR implementation of digital circuits and the ease of the test pattern generation for some AND-EXOR structures. Nevertheless, no evidence has been presented regarding the advantages of AND-EXOR minimal forms with respect to AND-OR logic in the problem of test generation. the present paper compares the number of test patterns required for testing switching functions which are implemented by AND-OR and AND-EXOR minimal expressions, respectively. Conclusions about the situations in which it is more advantageous to use one or the other logic are established from the analysis of these results.
the design and construction of a hardware fast Fourier transform processor are presented. the hardware relies principally on field programmable gate arrays (FPGAs). the hardware architecture is based on Tukey-Cooley b...
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A static induction transistor (SIT) has been applied to I**2L circuit technology. the I**2L equivalent static induction transistor logic (SITL) is evaluated by using type D F/F frequency divider and 14 bit BCD program...
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A static induction transistor (SIT) has been applied to I**2L circuit technology. the I**2L equivalent static induction transistor logic (SITL) is evaluated by using type D F/F frequency divider and 14 bit BCD programmable counter to prove its potentiality in VLSI. Operational frequency is over 20 MHz in the frequency divider and 10 MHz in the 14 bit BCD programmable counter with a power dissipation of a few hundreds microwatts. the normally-configurated SIT is introduced to serve as a driver transistor in the SITL having new circuit configuration in order to improve the speed performance, where output Schottky diodes are fabricated to ensure the decoupling between outputs. the performance of this Schottky SITL is evaluated by using the ring oscillator, where the propagation delay is 2. 5 nsec with a power dissipation of 100 mu W.
the paper presents a new remote laboratory for the development of programmablelogic experiments that allows to perform all the workflow included in the development of digital systems through programmable devices from...
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Anewmethod to implement threshold logic functions using memristors is presented. this method benefits from the high range of memristor's resistivity, which is used to define different weight values, and reduces si...
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Anewmethod to implement threshold logic functions using memristors is presented. this method benefits from the high range of memristor's resistivity, which is used to define different weight values, and reduces significantly the transistor count. When considering an upper bound on transistor count, the proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45-nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption.
A low power consumption, high-speed and wide division ratio range programmable frequency divider designed in 0.18 um SiGe process is presented. the circuit consists of 4/5 dual-modulus prescaler, 5-bit subtraction cou...
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ISBN:
(纸本)9781728189789
A low power consumption, high-speed and wide division ratio range programmable frequency divider designed in 0.18 um SiGe process is presented. the circuit consists of 4/5 dual-modulus prescaler, 5-bit subtraction counter and control logic. the combination of D flip-flops and logic gates effectively reduces the transmission delay and improves the operating frequency of the dual-modulus prescaler. the pulse counter and the swallow counter are merged into one, which reduces the chip area. A novel control logic is adopted to reduce the minimum frequency division ratio by allowing the S value equal to 0. the whole frequency divider is composed of TSPC (true-single-phase-clocked) D flip-flops and complementary CMOS logic gates without static power consumption. the simulation results indicate that the programmable frequency divider has a 4.7 GHz maximum operating frequency, and achieves a continuous division ratio range from 16 to 159, with a power consumption of 5.9 mA at 1.8 V supply voltage at the maximum operating frequency.
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