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检索条件"任意字段=5th Southern Conference on Programmable Logic"

共 391 条记录，以下是31-40 订阅

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Design of Low Power Consumption, High-Speed and Wide Division Ratio Range programmable Frequency Divider 5

Design of Low Power Consumption, High-Speed and Wide Divisio...

引用

5th International conference on Integrated Circuits and Microsystems (ICICM)

作者： Chen, Zhen Zhang, Youming Tang, Xusheng Li, Junjie Huang, Fengyi Jiang, Nan Southeast Univ Nanjing 210096 Peoples R China Purple Mt Labs Nanjing 211111 Peoples R China S TEK Reserch Ctr Shanghai 201203 Peoples R China

ISBN: (纸本)9781728189789

A low power consumption, high-speed and wide division ratio range programmable frequency divider designed in 0.18 um SiGe process is presented. the circuit consists of 4/5 dual-modulus prescaler, 5-bit subtraction counter and control logic. the combination of D flip-flops and logic gates effectively reduces the transmission delay and improves the operating frequency of the dual-modulus prescaler. the pulse counter and the swallow counter are merged into one, which reduces the chip area. A novel control logic is adopted to reduce the minimum frequency division ratio by allowing the S value equal to 0. the whole frequency divider is composed of TSPC (true-single-phase-clocked) D flip-flops and complementary CMOS logic gates without static power consumption. the simulation results indicate that the programmable frequency divider has a 4.7 GHz maximum operating frequency, and achieves a continuous division ratio range from 16 to 159, with a power consumption of 5.9 mA at 1.8 V supply voltage at the maximum operating frequency.

关键词： programmable frequency divider dual-modulus prescaler TSPC programmable counter

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the architecture of an FPGA-style programmable fuzzy logic controller chip 5

The architecture of an FPGA-style programmable fuzzy logic c...

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5th Australasian Computer Architecture conference, ACAC 2000

作者： Lund, T. Torralba, A. Carvajal, R.G. School of Computing University of Canberra ACT2601 Australia Dpto. de Ingenieria Electronica Escuela Superior de Ingenieros de Sevilla Camino de los Descubrimientos s/n Sevilla41092 Spain

ISBN: (纸本)0769505120

In the search for a fuzzy logic equivalent of the FPGA, the authors have developed the design for a programmable fuzzy logic controller chip which can accept up to 4 inputs, provide up to 12 programmable membership functions to fuzzify those inputs, and provide up to 8 programmable singleton values from which an output can be synthesised. Up to 64 rules can be evaluated simultaneously. the analogue modules which perform the fuzzification, rule evaluation and defuzzification operations are interconnected in a programmable fashion, modelled on the structure of FPGAs. this design will require an area of about 6 mm2 in 0.8 μm CMOS technology and draw about 9 mA. © 2000 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A Field programmable Process-In-Memory Architecture Based on RRAM Technology 5

A Field Programmable Process-In-Memory Architecture Based on...

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5th International conference on Mechanical, Control and Computer Engineering (ICMCCE)

作者： Liang, Yuan Yin, Longxiang Xu, Ning Wuhan Univ Technol Sch Comp Sci & Technol Wuhan Peoples R China Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Wuhan Univ Technol Sch Informat Engn Wuhan Peoples R China

ISBN: (纸本)9781665423144

Conventional reconfigurable architectures, e.g., Field-programmable Gate Array (FPGA), are confronted with the inflexibility of the on-chip local memory architecture and the scarce memory resource, which result in the inflexibility to deal with the current memory-thirsty data-intensive applications. Emerging nonvolatile devices, such as resistive random-access memory (RRAM), can operate in a logic-in-memory way, i.e., they can act as both a nonvolatile memory element and a switch, and thus, have the potential to provide higher flexibility and data processing ability. We propose a field-programmable logic-in-memory architecture based on RRAM technology, which is a two-dimensional tile array, where each tile is an RRAM-based crossbar array and can be remolded into three basic modes including logic, interconnect and memory. We further develop a specific adaptive algorithm for placement and routing, which can well exploit the logic-in-memory architecture characteristics. Comparing with traditional FPGAs, our architecture shows 1.9x lower power consumption, 2.8x lower delay, and 5.6x higher performance.

关键词： RRAM logic-in-memory reconfigurable P&R

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FMAP: A technology mapping algorithm for FPGA with MUX-LUT mixed architecture 5

FMAP: A technology mapping algorithm for FPGA with MUX-LUT m...

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5th International conference on ASIC

作者： Wen, YJ Tong, JR Chiang, C Fudan Univ Shanghai Peoples R China

ISBN: (纸本)078037889X

Because of its advantages of the short design turnaround time and the convenience and low cost in integrated circuit prototyping and verification. the field programmable gate array (FPGA) has been widely utilized in many fields of electronic design. In this paper, a technology mapping algorithm for FPGA with MUX-LUT mixed architecture is presented. this algorithm, FMAP, is used in a design-aided software system for FPGA, which is developed specifically for ail FPGA chip. FDP, with MUX-LUT mixed architecture. the bench marking result of technology mapping for FDP by FMAP is compared to the result of the Xilinx series by their design system. the result is also presented in this paper.

关键词： field programmable gate arrays integrated circuit design logic design table lookup

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FPGA-based transmit/receive distributed controller for the TR modules of an L band antenna (SAR)

FPGA-based transmit/receive distributed controller for the T...

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4th southern conference on programmable logic

作者： Siman, Javier Jaquenod, Guillermo Mascialino, Hugo DTA SA Monsenor Pablo Cabrera 5020X5008HJP Cordoba Argentina Comis Nacl Actividades Espaciales RA-1063 Buenos Aires DF Argentina

ISBN: (纸本)9781424419920

A Synthetic Aperture Radar (SAR) is built around a physical matrix of independent Transmit & Receive Modules (TRM). Each TRM has several parameters to be controlled to attain optimal performance and to compensate production dispersion and operation drift, and for calibration of the complete TR chain. the SAR is an instrument of the SAOCOM Low Earth Orbit satellite, which will be launched on 2010. It has 105 TRM, organized in 21 tiles, each one containing 5 TRM and a redundant controller. this paper presents the project and implementation of the redundant controller, based around a space qualified antifuse FPGA. this device was chosen after evaluation of SRAM, FLASH and antifuse technologies, and special considerations have been taken to reduce components count, minimize power consumption, cost, weight, and improve reliability.

关键词： Field programmable gate arrays (FPGA)

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An open source IEC 61131-3 integrated development environment

An open source IEC 61131-3 integrated development environmen...

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5th IEEE International conference on Industrial Informatics

作者： Tisserant, Edouard Bessard, Laurent de Sousa, Mario TBI SARL Lolitech F-88100 St Die France Univ Porto Dept Elect Engn Oporto Portugal

ISBN: (纸本)9781424408504

the IEC 61131-3 standard defines a common framework for programming PLCs (programmable logic Controllers), which includes the complete definition of four programming languages and a state machine definition language. Industrial PLC vendors are slowly offering support for this standard, however small inconsistencies remain between their implementations, transferring programs between vendors is almost impossible due to different rile formats, and licenses are generally too expensive to allow students do install these commercial solutions on their own computers. To this end, the authors have developed an Integrated Development Environment (IDE) for the IEC 61131-3 framework, which is being offered to the general public under the GNU Public License (GPL). the IDE consists of a Graphical User Interface (GUI) and a backend compiler. Using the GUI the user may develop programs in any of the four programming languages, as well as the state machine definition language. the backend compiler is used to convert these programs into equivalent C++ programs which may later be compiled and executed on various platforms.

关键词： programmable logic controllers

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Protocol for parallel communication between dissimilar controllers using discrete I/O: software implementation

Protocol for parallel communication between dissimilar contr...

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Proceedings of the 1996 5th Industrial Engineering Research conference

作者： Shelby, J.Mark Velasco, Tomas Southern Illinois Univ Carbondale United States

Many well - established manufacturers today find themselves using two or three different brands of programmable logic controllers. these controllers are usually networked for greater flexibility. However, as most controllers are designed to communicate only with others of the same brand, each brand requires its own network. the parallel protocol discussed in this paper is designed to provide high speed data transfer between networks of different brands of controllers regardless of architecture.

关键词： Network protocols

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Design of wind turbine generator control system

Design of wind turbine generator control system

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CES/IEEE 5th International Power Electronics and Motion Control conference

作者： Chen Guiyou Zhou Li Sun Tongjing Wang Zhongmin Shandong Univ Sch Control Sci & Engn Jinan Shandong Peoples R China

ISBN: (纸本)1424404487

the principle of wind turbine generator (WTG) and its control system based on programmable logic controller (PLC) are presented. the wind energy is converted into electric energy by WTG. Because of the uncertainties of the speed, the direction of the wind, and the large inertia of the wind turbine of WTG, reliable control strategies are adopted to assure the WTG to run normally under serious conditions. According to the special requirement of the control system of 55kW WTG, a gate method is used to get the precise measurement of the generator's speed. the generator can be merged into or disengaged from the power system safely by the control system. the crosswind protection of the wind turbine and casting loose automatically are also realized. the practical running results show that the control system is reliable.

关键词： wind turbine generator programmable logic controller gate method control system

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A new approach to synthesize multiple-output functions using reversible programmable logic array

A new approach to synthesize multiple-output functions using...

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19th International conference on VLSI Design held jointly with 5th International conference on Embedded Systems Design

作者： Chowdhury, Ahsan Raja Nazmul, Rumana Babu, Hafiz Md. Hasan Department of Computer Science and Engineering University of Dhaka Dhaka-1000 Bangladesh

ISBN: (纸本)0769525024

In this paper, a new realization for logic functions, namely Reversible programmable logic Array (RPLA), has been proposed. the proposed realization has the advantage of regularity as compared to the existing non-PLA reversible realizations. A minimization technique is also presented along with the realization of reversible PLA. Experimental results are also shown for benchmark functions for the above realization. © 2006 IEEE.

关键词： logic circuits

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A Project of Compiler for a Processor with programmable Accelerator 5th

A Project of Compiler for a Processor with Programmable Acce...

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5th International Young Scientist conference on Computational Science (YSC)

作者： Steinberg, Boris Ya. Bugliy, Anton P. Dubrov, Denis V. Mikhailuts, Yury V. Steinberg, Oleg B. Steinberg, Roman B. Southern Fed Univ Rostov Na Donu Russia

In the following work, a project for compiler that maps program loops onto a processor with programmable accelerator is presented. the processor with programmable architecture could be a system on a chip containing regular computational cores as well as a programmable circuit. A classification of loops according to information dependencies is suggested. For each loop class, the possibility and method for automatic organization of hardware support with an FPGA are examined. the compiler under study differs from the regular ones for the presence of a converter from C to the hardware description language as well as a driver library for data transfer between a CPU and accelerator.

关键词： reconfigurable architecture pipeline computations high-level synthesis parallelizing compiler high-level internal representation FPGA HDL

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