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检索条件"任意字段=5th Southern Conference on Programmable Logic"

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Design and implementation of a new FPGA architecture 5

Design and implementation of a new FPGA architecture

引用

5th International conference on ASIC

作者： Ma, XJ Tong, JR Fudan Univ Microelect Dept ASIC & Syst State Key Lab Shanghai 200433 Peoples R China

ISBN: (纸本)078037889X

FPGA is widely applied in datapath applications, so it's all important design issue to contrive FPGA architecture fit for datapath circuit implementation. In this paper, we described a new FPGA architecture -- FDEGA (Field-programmable Datapath Enhanced Gate Array). the LC of FDEGA is optimized for datapath implementation. and can be programmed as either combinational or sequential device. FDEGA has hierarchical interconnection architecture. A chip with 16*16 LC array has been fabricated, and the design of LC and interconnection has been tested, and circuit sample chosen from practical digital system design has been implemented in FDEGA. the result proves that our design of FDEGA is correct.

关键词： field programmable gate arrays logic design circuit optimisation FPGA architecture datapath applications datapath circuit implementation FDEGA field-programmable datapath enhanced gate array datapath implementation combinational device sequential device hierarchical interconnection architecture digital system design LC array

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FPGA implementation of a binary32 floating point cube root 9

FPGA implementation of a binary32 floating point cube root

引用

2014 9th southern conference on programmable logic, SPL 2014

作者： Guardia, Carlos Minchola Boemo, Eduardo School of Engineering Universidad Autónoma de Madrid Madrid Spain

ISBN: (纸本)9781479968480

this paper presents the implementation of a sequential hardware core to compute a single floating point cube root compliant with the current IEEE 754-2008 standard. the design is based on Newton-Raphson recurrence, reciprocal and cube root units are implemented. Optimal performance requires two iterations for reciprocal and one for cube root units obtaining an accurate approximation of +/-3 least significant bits. Our proposal is able to be performed up to 149 Mhz over Virtex5. the hardware cost occupies 230 Slices and 12 Dsp48s taking a latency of 19 clock cycles. © 2014 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Exploring logic block granularity in leakage tolerant FPGA

Exploring logic block granularity in leakage tolerant FPGA

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19th International conference on VLSI Design held jointly with 5th International conference on Embedded Systems Design

作者： Konar, Rajan Bharadwaj, Rajarshee Bhatia, Dinesh Balsara, Poras T. Center for Integrated Circuits and Systems University of Texas Dallas United States

ISBN: (纸本)0769525024

Exponential increase in static power has emerged as a critical challenge to FPGA architects in nanometer designs. the significant amount of underutilized resources both in spatial and temporal domain provides opportunities for effective power management. In this work, we carry out an in-depth trade-off analysis of various design goals in a power aware programmable architecture designed to mitigate standby leakage energy. We identify the optimum granularity of logic blocks at which standby leakage has to be controlled while optimizing trade-offs with other design goals. © 2006 IEEE.

关键词： Field programmable gate arrays

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Safety Fuzzy logic Controller with 2003 architecture implemented in FPGA 5

Safety Fuzzy Logic Controller with 2003 architecture impleme...

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5th International conference on Systems and Control, ICSC 2016

作者： Nadir, Fatima Ezzahra Bsiss, Mohammed Jbilou, Mohammed Amami, Benaissa Faculty of Sciences and Technology Tangier Morocco

ISBN: (纸本)9781467389532

the industrial sector requires not only the performance of systems in terms of quality, productivity and reliability, but also in terms of security. the implementation of Fuzzy logic Controller (FLC) in Field programmable Gate Array (FPGA) does not allow only the system reliability and reduce the controller conception life cycle, but also ensures a safety integrity level (SIL) which is required by the field of application and related to the control system architecture. Analysis of a safety fuzzy logic controller implemented in FPGA can be performed by different methods that are related to international standards (IEC 61508 [1] and ISA TR 84.0.0.2 [2]). this paper proposes the analysis of a safety fuzzy logic controller implemented in FPGA with 2003 architecture [3] using a qualitative and a quantitative analysis provided by these standards. the quantitative analysis is performed by the calculation of average probability of failure on demand (PFDavg) of safety related system to define its safety integrity level (SIL). the qualitative analysis is based on the Reliability Block Diagram method [4] and [5] and Fault three Analysis [5] and [6]. © 2016 IEEE.

关键词： Fault tree analysis

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three-Phase Induction Motors Efficiency Analysis Using a programmable Power Supply 15

Three-Phase Induction Motors Efficiency Analysis Using a Pro...

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15th IEEE Brazilian Power Electronics conference and 5th IEEE southern Power Electronics conference, COBEP/SPEC 2019

作者： De Oliveira, Cassio Alves Dos Santos Junior, Josemar Alves De Moraes Filho, Marcos Jose Pinheiro, Vinicius Marcos Da Siveira, Augusto W. Fleury Veloso Gomes, Luciano Coutinho Uberlândia MG Brazil Itumbiara GO Brazil

ISBN: (纸本)9781728141800

this paper presents a three-phase induction motors efficiency study based on technical standards. An experimental bench was developed using a high precision programmable power supply. Many experiments were performed applying different and predetermined loads. the machine's currents and voltages were measured to define the efficiency. thus, an experimental setup was developed and the tests were performed with a high precision programmable power supply so that the acquired data is very reliable. the experimental setup was designed to perform tests at specifics operating points, allowing to apply variable loads. © 2019 IEEE.

关键词： Efficiency

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Design and Simulation of RISC Processor Using Verilog 5

Design and Simulation of RISC Processor Using Verilog

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5th International conference on Inventive Research in Computing Applications, ICIRCA 2023

作者： Sudhanya, P. Kumar, Aryan Sharma, Tushar Agrawal, Akshat Srm Institute of Science and Technology Faculty of Engineering and Technology Department of Electronics and Communication Engineering Kattankulathur603203 India

ISBN: (纸本)9798350321425

Reduced Instruction Set Computer (RISC) Processors have recently become quite an important aspect of keeping up with all the advances in technology. this research presents a comprehensive study on the design and simulation of an improved RISC processor architecture on Field-programmable Gate Arrays (FPGAs). the objective is to enhance the performance, efficiency, and versatility of RISC processors by incorporating novel design techniques and optimizations. the proposed design mainly focuses on the improved design of the Arithmetic and logic Unit (ALU). the effectiveness of the proposed design is evaluated through extensive simulations. the results demonstrate significant improvements in performance in time and total power. the findings of this study indicate that the improved RISC processor design offers a promising approach to address the increasing demands of modern computing systems. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Performance evaluations of ReconfigME

Performance evaluations of ReconfigME

引用

5th IEEE International conference on Field programmable Technology

作者： Wigley, Grant Kearney, David Univ South Australia Reconfigurable Comp Lab Mawson Lakes SA 5021 Australia

ISBN: (纸本)9780780397286

With the development of reconfigurable computers containing FPGAs with in excess of 6 million system-gates, it is now feasible to consider the possibility of sharing the FPGA between multiple concurrently executing applications. this could potentially increase the resource usage of the expensive FPGA logic and decrease response times so users will not have to wait for the FPGA to be completely available. However the system environment software required to support this, may actually result in application performance much less than would be considered acceptable to many FPGA users. this paper involves using a prototype to evaluate the performance of such an operating system, ReconfigME.

关键词： Field programmable gate arrays (FPGA)

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A FPGA-based voltage regulation control unit for optical phased array beam deflector 5

A FPGA-based voltage regulation control unit for optical pha...

引用

5th International conference on ASIC

作者： Gong, XD Li, JZ Li, SX Liu, CP Shenzhen Univ Dept Photon Informat Engn Shenzhen 518060 Peoples R China

ISBN: (纸本)078037889X

the hardware design and FPGA implementation of a voltage regulation control unit for optical phased array beam deflector is described. With the control unit used for a 16-channel waveguide phased array beam deflector, a beam scan rate above 500 kHz can be achieved, which is far higher than that obtained with other implementation methods based on microcontrollers.

关键词： optical deflectors optical arrays voltage regulators field programmable gate arrays logic design voltage regulation control unit optical phased array beam deflector FPGA implementation waveguide phased array beam deflector beam scan rate microcontrollers

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A Fully logic CMOS Compatible Non-Volatile Memory for Low Power IoT Applications 5

A Fully Logic CMOS Compatible Non-Volatile Memory for Low Po...

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5th International conference on the Internet of things (IOT)

作者： Wang, Yu Xiang, Junhui Chen, Xianliang Yang, Tao Yan, Na Min, Hao Fudan Univ State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9781467380584

this paper presents a 512-bit low power electrically programmable embedded non-volatile memory (eNVM) for the Internet of things (IoT) applications. A novel memory bit cell which is fully compatible to the CMOS logic process is developed using dual tunneling gate structure. Costumer designed lateral double diffused MOS transistor (LDMOS) is proposed in a novel high voltage management circuit to improve the reliability and safety of the memory established by thin gate oxide transistors. In charge pump design, a frequency step-up scheme is proposed to control the current surge during writing operation, thus large voltage droops in the power supply is prevented, improving the stability of the system. the memory is implemented in a standard 0.13 mu m CMOS technology process. Measured results indicate that under the supply voltage of 1.2 V, it consumes 9.2 mu W (22.9 mu W) at the read (write) rate of 6.78 Mb/s (8 kb/s). Endurance characteristics under 100k program cycles stress test and data retention characteristics of up to 10 years are demonstrated.

关键词： eNVM logic CliaS compatible dual tunneling gate LDMOS frequency step-up charge pump low power

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Field programmable gate array (FPGA) implementation of digital systems: An alternative to ASIC 5

Field programmable gate array (FPGA) implementation of digit...

引用

5th International conference on VLSI Design, ICVD 1992

作者： Srini, Vason P. Dataflow Systems 986 Cragmont Ave BerkeleyCA94708 United States

ISBN: (纸本)0818624655

Rapid prototyping and simulation of digital systems using arrays of field programmable gate array (FPGA) chips is expected to be an important aspect of digital design and implementation. Four classes of architectures are discussed for connecting an array of FPGA chips and also logic blocks in a chip to achieve functionality and performance comparable to that of ASIC designs using standard cells and mask programmable gate arrays and at a low cost and reduced development time. the four classes of architectures use technologies such as anti- fuse, SRAM, Electrically Erarable PROM (EEPROM), and (Ultraviolet) Erasable PROM (EPROM) to control and configure interconnection structures between the logic blocks. the software requirements for these classes of architectures and potential performance are discussed. the impact of these architectures on commercial products is also described. © 1991 IEEE.

关键词： Field programmable gate arrays (FPGA)

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