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9th acm sigplan symposium on principles and practice of parallel programming

作者： McCurdy, C Fischer, C Univ Wisconsin Dept Comp Sci Madison WI 53706 USA

ISBN: (纸本)9781581135886

In programming high performance applications, shared address-space platforms are preferable for fine-grained computation, while distributed address-space platforms are more suitable for coarse-grained computation. However, currently only distributed address-space systems scale beyond the low hundreds of processors. In this paper we introduce a hybrid architecture that allows users to trade off local memory usage for coherence communication, making possible larger-scale shared memory architectures. We introduce a programming model and examine possible implementations of hardware mechanisms, evaluating some of the trade-offs inherent in each. Preliminary experiments on an application with particularly fine-grained communication requirements indicate that effective placement of directives can reduce coherence communication by more than a factor of 10 for 64 processors.

关键词： performance design languages parallel computation shared memory architectures distributed memory architectures irregular computation

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Space-efficient implementation of nested parallelism

Space-efficient implementation of nested parallelism

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Proceedings of the 1997 6th acm sigplan symposium on principles and practice of parallel programming

作者： Narlikar, Girija J. Blelloch, Guy E. CMU Sch of Computer Science Pittsburgh United States

Many of today's high level parallel languages support dynamic, fine-grained parallelism. these languages allow the user to expose all the parallelism in the program, which is typically of a much higher degree than the number of processors. Hence an efficient scheduling algorithm is required to assign computations to processors at runtime. Besides having low overheads and good load balancing, it is important for the scheduling algorithm to minimize the space usage of the parallel program. this paper presents a scheduling algorithm that is provably space-efficient and time-efficient for nested parallel languages. In addition to proving the space and time bounds of the parallel schedule generated by the algorithm, we demonstrate that it is efficient in practice. We have implemented a runtime system that uses our algorithm to schedule parallel threads. the results of executing parallel programs on this system show that our scheduling algorithm significantly reduces memory usage compared to previous techniques, without compromising performance.

关键词： parallel processing systems

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parallel and Distributed Bounded Model Checking of Multi-threaded Programs 20

Parallel and Distributed Bounded Model Checking of Multi-thr...

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25th acm sigplan symposium on principles and practice of parallel programming (PPoPP)

作者： Inverso, Omar Trubiani, Catia Gran Sasso Sci Inst Laquila Italy

ISBN: (纸本)9781450368186

We introduce a structure-aware parallel technique for context-bounded analysis of concurrent programs. the key intuition consists in decomposing the set of concurrent traces into symbolic subsets that are separately explored by multiple instances of the same decision procedure running in parallel. the decision procedures work on different partitions of the search space without cooperating, whence distribution follows effortlessly. Our experiments on a selection of complex multi-threaded programs show significant analysis speedups and scalability, and greater performance gains than with general-purpose parallel solvers.

关键词： Concurrency Multithreading Sequentialization Software Verification parallel Analysis Bounded Model Checking SAT

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the Boat Hull Model: Adapting the Roofline Model to Enable Performance Prediction for parallel Computing 12

The Boat Hull Model: Adapting the Roofline Model to Enable P...

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17th acm sigplan symposium on principles and practice of parallel programming

作者： Nugteren, Cedric Corporaal, Henk Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9781450311601

Multi-core and many-core were already major trends for the past six years, and are expected to continue for the next decades. With these trends of parallel computing, it becomes increasingly difficult to decide on which architecture to run a given application. In this work, we use an algorithm classification to predict performance prior to algorithm implementation. For this purpose, we modify the roofline model to include class information. In this way, we enable architectural choice through performance prediction prior to the development of architecture specific code. the new model, the boat hull model, is demonstrated using a GPU as a target architecture. We show for 6 example algorithms that performance is predicted accurately without requiring code to be available.

关键词： Performance parallel computing performance prediction many-core accelerators the roofline model

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Provably good scheduling for parallel programs that use data structures through implicit batching 14

Provably good scheduling for parallel programs that use data...

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2014 19th acm sigplan symposium on principles and practice of parallel programming, PPoPP 2014

作者： Agrawal, Kunal Fineman, Jeremy T. Sheridan, Brendan Sukha, Jim Utterback, Robert Washington University in Saint Louis United States Georgetown University United States Intel Corporation United States

this poster proposes an efficient runtime scheduler that provides provable performance guarantees to parallel programs that use data structures through the use of implicit batching.

ISBN: (纸本)9781450326568

this poster proposes an efficient runtime scheduler that provides provable performance guarantees to parallel programs that use data structures through the use of implicit batching.

关键词： Data structures

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Swift/T: Scalable Data Flow programming for Many-Task Applications 13

Swift/T: Scalable Data Flow Programming for Many-Task Applic...

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18th acm sigplan symposium on principles and practice of parallel programming

作者： Wozniak, Justin M. Armstrong, Timothy G. Wilde, Michael Katz, Daniel S. Lusk, Ewing Foster, Ian T. Argonne Natl Lab Argonne IL 60439 USA Univ Chicago Chicago IL 60637 USA

Swift/T, a novel programming language implementation for highly scalable data flow programs, is presented.

ISBN: (纸本)9781450319225

Swift/T, a novel programming language implementation for highly scalable data flow programs, is presented.

关键词： Languages MPI ADLB Swift Turbine exascale concurrency dataflow futures

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Turbocharging Boosted Transactions or: How I Learnt to Stop Worrying and Love Longer Transactions

Turbocharging Boosted Transactions or: How I Learnt to Stop ...

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Kulkarni, Chinmay Unsal, Osman Cristal, Adrian Ayguade, Eduard Valero, Mateo Birla Inst Technol & Sci Pilani Rajasthan India Tech Univ Catalunya Catalunya Spain

ISBN: (纸本)9781605583976

Boosted transactions offer an attractive method that enables programmers to create larger transactions that scale well and offer deadlock-free guarantees. However, as boosted transactions get larger, they become more susceptible to conflicts and aborts. We describe a linear-time algorithm to detect transactions that cannot make progress, which transactions need to be aborted, and when. the algorithm guarantees zero false positives with minimal aborts. Our proposals, as implemented in DSTM2, increase the transactional throughput of the system, often by more than 30%.

关键词： Algorithms Performance Concurrency parallel programming transactional memory deadlocks deadlock-detection

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Preliminary Results on NB-FEB, a Synchronization Primitive for parallel programming

Preliminary Results on NB-FEB, a Synchronization Primitive f...

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14th acm sigplan symposium on principles and practice of parallel programming

作者： Ha, Phuong Hoai Tsigas, Philippas Anshus, Otto J. Univ Tromso N-9001 Tromso Norway Chalmers Univ Technol Gothenburg Sweden

ISBN: (纸本)9781605583976

We introduce a non-blocking full/empty bit primitive, or NB-FEB for short, as a promising synchronization primitive for parallel programming on may-core architectures. We show that the NB-FEB primitive is universal, scalable and feasible. NB-FEB, together with registers, can solve the consensus problem for an arbitrary number of processes (universality). NB-FEB is combinable, namely its memory requests to the same memory location can be combined into only one memory request, which consequently mitigates performance degradation due to synchronization "hot spots" (scalability). Since NB-FEB is a variant of the original full/empty bit that always returns a value instead of waiting for a conditional flag, it is as feasible as the original full/empty bit, which has been implemented in many computer systems (feasibility).

关键词： Algorithms Reliability theory many-core architectures non-blocking synchronization full/empty bit universal primitives combinability

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Energy-optimal configuration selection for manycore chips with variation

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2017年第5期31卷 451-466页

作者： Langer, Akhil Totoni, Ehsan Palekar, Udatta Kale, Laxmikant V. Intel Fed 1906 Fox Dr Champaign IL 61820 USA Univ Illinois Coll Business Urbana IL 61801 USA Univ Illinois Dept Comp Sci 1304 W Springfield Ave Urbana IL 61801 USA

Operating chips at high energy efficiency is one of the major challenges for modern large-scale supercomputers. Low-voltage operation of transistors increases the energy efficiency but leads to frequency and power variation across cores on the same chip. Finding energy-optimal configurations for such chips is a hard problem. In this work, we study how integer linear programming techniques can be used to obtain energy-efficient configurations of chips that have heterogeneous cores. Our proposed methodologies give optimal configurations as compared with competent but sub-optimal heuristics while having negligible timing overhead. the proposed ParSearch method gives up to 13.2% and 7% savings in energy while causing only 2% increase in execution time of two HPC applications: miniMD and Jacobi, respectively. Our results show that integer linear programming can be a very powerful online method to obtain energy-optimal configurations.

关键词： energy power optimization multicore chips low-voltage computing near-threshold voltage computing process variation heterogeneity integer programming quadratic integer programming

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L2C2: Logic-based LSC Consistency Checking

L2C2: Logic-based LSC Consistency Checking

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11th International acm sigplan symposium on principles and practice of Declarative programming (PPDP 09)

作者： Guo, Hai-Feng Zheng, Wen Subramaniam, Mahadevan Univ Nebraska Dept Comp Sci Omaha NE 68182 USA

ISBN: (纸本)9781605585680

Live sequence charts (LSCs) have been proposed as an inter-object scenario-based specification and visual programming language for reactive systems. In this paper, we introduce a logic-based framework to check the consistency of an LSC specification. An LSC simulator has been implemented in logic programming, utilizing a memoized depth-first search strategy, to show how a reactive system in LSCs would response to a set of external event sequences. A formal notation is defined to specify external event sequences, extending the regular expression with a parallel operator and a testing control. the parallel operator allows interleaved parallel external events to be tested in LSCs simultaneously;while the testing control provides users to a new approach to specify and test certain temporal properties (e.g., CTL formula) in a form of LSC. Our framework further provides either a state transition graph or a failure trace to justify the consistency checking results.

关键词： live sequence chart (LSC) scenario-based programming PLAY-tree logic programming memoization

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