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检索条件"任意字段=6th International Symposium on Code Generation and Optimization"

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6th international Conference on Cyber Security Intelligence and Analytics, CSIA 2024

6th International Conference on Cyber Security Intelligence ...

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6th international Conference on Cyber Security Intelligence and Analytics, CSIA 2024

ISBN: (纸本)9783031882869

the proceedings contain 56 papers. the special focus in this conference is on Cyber Security Intelligence and Analytics. the topics include: Comparative Study of ARIMA Model and Long Short Term Memory Network (LSTM) in Economic Management;the Application and Empirical Study of Causality in the theory Graph;research on Machining and Simulation optimization System of Automobile Steering Knuckle Based on Advanced Algorithm;network Partitioning and Demand Characterization for Management of Urban Low Voltage Power Distribution Systems;automation and Data Aggregation Algorithm for Low code Development in Power Grid Mobile Report generation;big Data Analysis and Smart Grid Security Event Monitoring and Response in the Power Internet of things;Construction of an Online Autonomous Learning Model Based on Artificial Intelligence ChatGPT;Application of PMS Graphic Intelligent Recognition and Analysis Based on Contact Diagram Automatic generation Technology;application of Genetic Algorithm in Reasonableness Evaluation of Environmental Design Space Layout;construction of an Intelligent Recommendation Model for Digital Media Content Based on Artificial Intelligence;research on Link Selection and Allocation for IoT Localization Systems Based on an Improved Ant Colony Algorithm;cross-Domain Sharing and Privacy Protection Method of Fused Multi-source Data in Visual Internet of things;construction of Cold Chain Logistics and Distribution Site Selection System Based on Multi-objective optimization Model;hole Detection Algorithm Based on Channel Fusion Siamese Network;intelligent Database Triggers Enable Advanced Analysis of Data Recorded in Audit Logs;improvement of Principal Component Analysis Algorithm and Its Simulation Experiment;OLAP Technology Financial Statistics Information Platform Based on Big Data Analysis.

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Enhancing synergy for power generation and coastal protection through wave energy converters 6th

Enhancing synergy for power generation and coastal protectio...

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6th international Conference on Renewable Energies Offshore, RENEW 2024

作者： Battisti, B. Giorgi, G. Fernandez, G. Verao Politecnico di Torino Italy Université de Bordeaux IMB France Department of the Built Environment Aalborg University Denmark

ISBN: (纸本)9781032905570

Combining efforts to promote both power generation and coastal protection would offer significant advantages for the marine sector. It presents an opportunity to combine resources for the dual purpose of adapting to the effects of climate change, and producing clean energy, thereby potentially fostering growth in the blue economy. Wave Energy Converters (WECs), and particularly WEC farms, are ideally suited to fulfill this dual role, as they can harvest energy from waves, thus also mitigating their impact on coastlines, with the generation of milder waves in their lee. this research investigates the impact of a small WEC farm on both objectives. Different strategies are proposed, and compared, to address this dual focus. Strategies may involve establishing a minimum threshold for wave attenuation, while maximizing power production, and others aim to optimize both power production, and wave attenuation simultaneously. the former strategies can be easily tailored to meet specific coastal protection requirements, at a particular site. the latter entail addressing a bi-objective optimization problem, with two concurrent objectives. this paper explores these different approaches, ultimately laying the groundwork for a comprehensive multi-query analysis of WEC farms. © 2025 the Author(s).

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6th international Conference on Security and Privacy in New Computing Environments, SPNCE 2023

6th International Conference on Security and Privacy in New ...

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6th international Conference on Security and Privacy in New Computing Environments, SPNCE 2023

ISBN: (纸本)9783031736988

the proceedings contain 23 papers. the special focus in this conference is on Security and Privacy in New Computing Environments. the topics include: Consortium Blockchain Storage optimization Based on Fountain codes;an Incentive Mechanism and An Offline Trajectory Publishing Algorithm Considering Sensing Area Coverage Maximization and Participant Privacy Level;Research on Face Recognition System Based on RLWE Homomorphic Encryption;feedback Feed-Forward Iterative Learning Control for Non-affine Nonlinear Discrete-Time Systems with Varying Trail Lengths;open-Closed-Loop Iterative Learning Control Based on Differential Evolution Algorithm for Nonlinear System;overview of Vehicle Edge Computing and Its Security;conFlow: Contrast Network Flow Improving Class-Imbalanced Learning in Network Intrusion Detection;anomaly Detection of Unstable Log Data Based on Contrastive Learning;An Integration-Enhanced ZNN Approach for Chaotic Combination Synchronization with External Disturbances∗;a Lightweight Anomaly Detection Method for Industrial Processes Based on Event Correlation Behavior;a Novel Polar code-Based Key Encapsulation Mechanism with Non-permutation Equivalent Public Key;two-Stage Multi-lingual Speech Emotion Recognition for Multi-lingual Emotional Speech Synthesis;EncoderMU: Machine Unlearning in Contrastive Learning;NoCrypto: A Web Mining Behavior Detection Method Based on RGB Images;image Copy-Move Forgery Detection in the Social Media Based on a Prior Density Clustering and the Point Density;detection of Speech Spoofing Based on Dense Convolutional Network;speech Emotion Recognition Based on Recurrent Neural Networks with Conformer for Emotional Speech Synthesis;Route Privacy-Preserving Authentication Scheme Based on PUF in VANETs;Stable NICE Model-Based Picture generation for Generative Steganography;computer-Generated Image Forensics Based on Vision Transformer with Forensic Feature Pre-processing Module;VoIP Steganalysis Using Shallow Multiscale Convolution and

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Compiling for Vector-thread Architectures 08

Compiling for Vector-Thread Architectures

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6th international symposium on code generation and optimization

作者： Hampton, Mark Asanovic, Krste MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

ISBN: (纸本)9781595939784

Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. this paper describes a compiler for the Scale VT architecture, which takes advantage of the VT features. We focus oil compiling loops, and show how the compiler call transform code that poses difficulties for traditional vector or VLIW processors, such as loops with internal control flow or cross-iteration dependences, while still taking advantage of features not supported by multi-threaded designs, such as vector memory instructions. We evaluate the compiler using several embedded benchmarks and show that we can obtain substantial speedups over a single-issue, in-order scalar machine.

关键词： Vector processors Compilers code generation

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Phase-Based Adaptive Recompilation in a JVM 08

Phase-Based Adaptive Recompilation in a JVM

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6th international symposium on code generation and optimization

作者： Gu, Dayong Verbrugge, Clark McGill Univ Sch Comp Sci Montreal PQ Canada

ISBN: (纸本)9781595939784

Modern JIT compilers often employ multi-level recompilation strategies as a means of ensuring the most used code is also the most highly optimized, balancing optimization costs and expected future performance. Accurate selection of code to compile and level of optimization to apply is thus important to performance. In this paper we investigate the effect of an improved recompilation strategy for a Java virtual machine. Our design makes use of a lightweight, low-level profiling mechanism to detect high-level, variable length phases in program execution. Phases are then used to guide adaptive recompilation choices, improving performance. We develop both an offline implementation based on trace data and a self-contained online version. Our offline study shows an average speedup of 8.7% and up to 21%, and our online system achieves an average speedup of 4.4%, tip to 18%. We subject our results to extensive analysis and show that our design achieves good overall performance with high consistency despite the existence of many complex and interacting factors in such art environment.

关键词： Virtual machine Java adaptive optimization runtime technique hardware counters

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COLE: Compiler optimization Level Exploration 08

COLE: Compiler Optimization Level Exploration

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6th international symposium on code generation and optimization

作者： Hoste, Kenneth Eeckhout, Lieven Univ Ghent ELIS Dept B-9000 Ghent Belgium

ISBN: (纸本)9781595939784

Modern compilers implement a large number of optimizations which all interact in complex ways, and which all have a different impact oil code quality, compilation time, code size, energy consumption, etc. For this reason, compilers typically provide a limited number of standard optimization levels, such as -01, -02, -03 and -0s, that combine various optimizations providing a number of trade-offs between multiple objective functions (such as code quality, compilation time and code size). the construction of these optimization levels, i.e., choosing which optimizations to activate at each level, is a manual process typically done using high-level heuristics based on the compiler developer's experience. this paper proposes COLE, Compiler optimization Level Exploration, a framework or automatically finding Pareto optimal optimization levels through multi-objective evolutionary searching. Our experimental results using GCC and the SPEC CPU benchmarks show that the automatic construction of optimization levels is feasible in practice, and in addition, yields better optimization levels than GCC's manually derived (-0s, -01, -02 and -03) optimization levels, as well as the optimization levels obtained through random sampling. We also demonstrate that COLE can be used to gain insight into the effectiveness of compiler optimizations as well as to better understand a benchmark's sensitivity to compiler optimizations.

关键词： compiler optimization multi-objective search

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Automatic Array Inlining in Java Virtual Machines 08

Automatic Array Inlining in Java Virtual Machines

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6th international symposium on code generation and optimization

作者： Wimmer, Christian Moessenboeck, Hanspeter Johannes Kepler Univ Linz Inst Syst Software Christian Doppler Lab Automated Software Engn A-4040 Linz Austria

ISBN: (纸本)9781595939784

Array inlining expands the concepts of object inlining to arrays. Groups of objects and arrays that reference each other are placed consecutively in memory so that their relative offsets are fixed, i.e. they are colocated. this allows memory loads to be replaced by address arithmetic, which reduces the costs of field and array accesses. We implemented this optimization for Sun Microsystems' Java HotSpot (TM) VM. the optimization is performed automatically and requires no actions on the part of the programmer. Arrays are frequently used for the implementation of dynamic data structures. therefore, the length of arrays often varies, and fields referencing such arrays have to be changed whenever the array is reallocated. We present an efficient code pattern that detects these changes and allows the optimized access of such array fields. It is integrated into the array bounds check. We also claim that inlining array element objects into an array is not possible without a global data flow analysis. the evaluation shows that our dynamic approach can optimize frequently accessed fields with a reasonable low compilation and analysis overhead. the peak performance of SPECjvm98 is improved by 10% on average, with a maximum of 25%.

关键词： Java object inlining array inlining just-in-time compilation garbage collection optimization performance

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Latency-Tolerant Software Pipelining in a Production Compiler 08

Latency-Tolerant Software Pipelining in a Production Compile...

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6th international symposium on code generation and optimization

作者： Winkel, Sebastian Krishnaiyer, Rakesh Sampson, Robyn Intel Corp Intel Compiler Lab Santa Clara CA USA

ISBN: (纸本)9781595939784

In this paper we investigate the benefit of scheduling non-critical loads for a higher latency during software pipelining. "Non-critical" denotes those loads that have sufficient slack in the cyclic data dependence graph so that increasing the scheduling distance to their first use can only increase the number of stages of the software pipeline, but should not increase the lengths of the individual stages, the initiation interval (11). the associated cost is in many cases negligible, but the memory stall reduction due to improved latency coverage and load clustering in the schedule can be considerable. We first analyze benefit and cost in theory and then present how we have implemented latency-tolerant pipelining experimentally in the Intel Itanium (R) product compiler. A key component of the technique is the preselection of likely long-latency loads that is integrated into prefetching heuristics in the high-level optimizer. Only when applied selectively based on these prefetcher hints, the optimization gives the full benefit also without trip-count information from dynamic profiles. Experimental results show gains of up to 14%, with an average of 2.2%, in a wide range of SPEC (R) CPU2000 and CPU2006 benchmarks. these gains were realized on top of best-performing compiler options typically used for SPEC submissions.

关键词： load clustering compiler memory-level parallelism modulo scheduling itanium latency-tolerant scheduling software pipelining code generation prefetching memory latency epic

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Removing Redundancy via Exception Check Motion 08

Removing Redundancy via Exception Check Motion

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6th international symposium on code generation and optimization

作者： Sundaresan, Vijay Stoodley, Mark Ramarao, Pramod IBM Canada Ltd Markham ON L6G 1C7 Canada

ISBN: (纸本)9781595939784

Partial redundancy elimination aims to reduce the number of times an expression is computed more than once. the traditional Lazy code Motion (LCM) algorithm formulated by Knoop, Ruthing and Steffen, through its reliance on unordered bit vectors, is severely limited in its ability to remove redundancy when precise exception semantics are required because bit vectors cannot express the order of exception checks. this paper describes our new PRE algorithm Exception Check Motion that uses the LCM algorithm to treat and optimize exception checks in a similar way to any other expression. Unlike earlier techniques that can remove only the compare instruction of a partially redundant exception check, our solution can eliminate both the compare and trap instructions without any run time code patching or expensive recovery operations. Since it is the trap instructions that restrict subsequent code motions, our technique gives downstream optimizations more flexibility to improve the performance of the resulting code once the partially redundant checks are eliminated. Our analysis has been implemented in the IBM (R) Testarossa (TM) (TR) just-in-time (JIT) compiler in the IBM Developer Kit for Java (TM) Release 5.0 as part of the J9 Virtual Machine. We measure performance improvements up to 7.6% and averaging 2.5% across 22 SPEC and DaCapo benchmarks on 4-way IBM pSeries (PowerPC) hardware.

关键词： Java (TM) Just-in-time compilation Partial redundancy elimination

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Comprehensive Path-sensitive Data-flow Analysis 08

Comprehensive Path-sensitive Data-flow Analysis

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6th international symposium on code generation and optimization

作者： thakur, Aditya Govindarajan, R. Indian Inst Sci Supercomp Educ & Res Ctr Bangalore 560012 Karnataka India

ISBN: (纸本)9781595939784

Data-flow analysis is an integral part of any aggressive optimizing compiler. We propose a framework for improving the precision of data-flow analysis in the presence of complex control-flow. We initially perform data-flow analysis to determine those control-flow merges which cause the loss in data-flow analysis precision. the control-flow graph of the program is then restructured such that performing data-flow analysis on the resulting restructured graph gives more precise results. the proposed framework is both simple, involving the familiar notion of product automata, and also general, since it is applicable to any forward data-flow analysis. Apart from proving that our restructuring process is correct, we also show that restructuring is effective in that it necessarily leads to more optimization opportunities. Furthermore, the framework handles the trade-off between the increase in data-flow precision and the code size increase inherent in the restructuring. We show that determining an optimal restructuring is NP-hard, and propose and evaluate a greedy strategy. the framework has been implemented in the Scale research compiler, and instantiated for the specific problem of Constant Propagation. On the SPECINT 2000 benchmark suite we observe an average speedup of 4% in the running times over Wegman-Zadeck conditional constant propagation algorithm and 2% over a purely path profile guided approach.

关键词： code Duplication Data-flow analysis Destructive Merge Path-sensitive Precision Restructuring Split Graph

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