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共 219 条记录，以下是41-50 订阅

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Optimizing a calibration software for radio astronomy 16

Optimizing a calibration software for radio astronomy

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16th IEEE Int Conf on High Performance Computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Madougou, Souley Varbanescu, Ana L. van Nieuwpoort, Rob Univ Amsterdam IvI Amsterdam Netherlands Netherlands eSci Ctr Amsterdam Netherlands

ISBN: (纸本)9781479961238

With the turn to multicore in chip design and manufacturing, both consumer and high performance applications can benefit from ubiquitous hardware parallelism. However, the performance improvement to be achieved is not always in the orders of magnitude range. In this paper, we present the challenging example of designing a parallel version of a model fitting algorithm used in calibrating telescope observation data in radio astronomy. the complexity of the application, together with the limited opportunities for code modification, bound the performance gain that any parallel system could achieve. However, we show how classical bound-and-bottleneck analysis and optimization using multicore architectures help achieving up to 2.3x "wallclock" speedup compared to the original sequential implementation. We further discuss the reasons for this limitation, and suggest possible solutions to address it.

关键词： code optimization model fitting multicore architecture parallel computing radio astronomy radio astronomy code optimization mode matching PARALLEL PROCESSING (COMPUTERS) Multi-core processors chip scale packaging parallel system

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Link-Time optimization for Power Efficiency in a Tagless Instruction Cache

Link-Time Optimization for Power Efficiency in a Tagless Ins...

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9th Annual IEEE/ACM international symposium on code generation and optimization (CGO)

作者： Jones, Timothy M. Bartolini, Sandro Maebe, Jonas Chanet, Dominique Univ Edinburgh Sch Infonnat Edinburgh EH8 9YL Midlothian Scotland Univ Siena Fac Engn Siena Italy Univ Ghent ELIS Dept Ghent Belgium Gateway Architecture Grp Technicolor Edegem Belgium

ISBN: (纸本)9781612843551

the instruction cache is a critical component in any microprocessor. It must have high performance to enable fetching of instructions on every cycle. However, current designs waste a large amount of energy on each access as tags and data banks from all cache ways are consulted in parallel to fetch the correct instructions as quickly as possible. Existing approaches to reduce this overhead remove unnecessary accesses to the data banks or to the ways that are not likely to hit. However, tag banks still need to be checked. this paper considers a new hybrid hardware and linker-assisted approach to tagless instruction caching. Our novel cache architecture, supported by the compilation toolchain, removes the need for tag checks entirely for the majority of cache accesses. the linker places frequency-executed instructions in specific program regions that are then mapped into the cache without the need for tag checks. this requires minor hardware modifications, no ISA changes and works across cache configurations. Our approach keeps the software and hardware independent, resulting in both backward and forward compatibility. Evaluation on a superscalar processor with and without SMT support shows power savings of 66% within the instruction cache with no loss of performance. this translates to a 49% saving when considering the combined power of the instruction cache and translation lookaside buffer, which is involved in managing our tagless scheme.

关键词： instruction cache Cache memory Data banks TAGGING dynamic efficiency energy capacity instruction translation lookaside buffer superscalar processor combined dynamic fetch Connector Device Component

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An Industrial Design Methodology for the Synthesis of OCV-Aware Top-Level Clock Tree 6

An Industrial Design Methodology for The Synthesis of OCV-Aw...

引用

6th international symposium on Next generation Electronics (ISNE)

作者： Kao, Hsu-Yu Lee, Yu Huang, Shih-Hsu Cheng, Wei-Kai Chou, Yih-Chih Chung Yuan Christian Univ Dept Elect Engn Taoyuan Taiwan Chung Yuan Christian Univ Dept Informat & Comp Engn Taoyuan Taiwan Global Unichip Corp Phys Design Methodol Dept Taipei Taiwan

ISBN: (纸本)9781538630969

In modern VLSI Design, on-chip-variation (OCV) has become serious as the feature size continues to shrink. Especially, in the top-level clock tree, OCV-induced clock skew should be properly controlled because of long wires. In this paper, we present a practical industrial design methodology for minimizing the OCV-induced clock skew of top-level clock tree. Our basic idea is to pre-place guide buffers for clock tree synthesis so that wire lengths of non-common paths can be reduced. We develop a novel algorithm to determine the number and the locations of guide buffers. Experiments with an industry chip show that our approach can greatly reduce the percentages of non-common paths (in the overall path) and thus the reduction on OCV-induced clock skew achieves 42.4%.

关键词： Clocks Design methodology Tools Wires Algorithm design and analysis optimization Urban areas

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Check-irregular LDPC codes for unequal error protection under iterative decoding 6

Check-irregular LDPC codes for unequal error protection unde...

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6th international ITG-Conference on Source and Channel Coding and 2006 4th international symposium on Turbo codes and Related Topics, TURBOCODING 2006

作者： Ssatelli, Lucile S.A Henkel, Werner Oeclercq, Oavid International University Bremen Campus Ring 1 Bremen28759 Germany ETIS ENSEA/UCP/CNRS UMR-8051 6 avenue du Ponceau Cergy95014 France

ISBN: (纸本)9783800729470

In many optimization techniques of LOPC codes, the check node irregularity is usually considered as being fixed because the profile must contain only two consecutive degrees in order to maximize the overall convergence speed of the code. We show in this paper that it is possible to construct bit-regular codes with more than two different degrees at check nodes side to speed up the convergence of some parts of the codeword, even if we may decrease a little the global convergence. then, we take advantage of the check irregularity to create unequal error protection (UEP) codes, and present a very flexible method to achieve it. this method is based on pruning a mother code, thereby creating different subcodes with different UEP properties, but decoded with the same decoder.

关键词： Iterative decoding

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Using binary images of non binary LDPC codes to improve overall performance 4

Using binary images of non binary LDPC codes to improve over...

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6th international ITG-Conference on Source and Channel Coding and 2006 4th international symposium on Turbo codes and Related Topics, TURBOCODING 2006

作者： Poulliat, Charly Fossorier, Marc Declercq, David ETIS ENSEA/UCP/CNRS 6 Avenue du Ponceau Cergy-PontoiseF-95014 France Coding Group Electrical Eng. Dept. University of Hawaii at Manoa 2540 Dole Str. HonoluluHI96822 United States

In this paper, we address the problem of the optimization of non binary LDPC codes for finite lengths. Using the binary image of the code, we provide a method for both waterfall and error floor improvements based on t... 详细信息

ISBN: (纸本)9783800729470

关键词： Binary images

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Impact of Non-Simultaneous P/f and Q/V Grid code Requirements on PV Inverters on Unintentional Islanding Operation in Distribution Network 6

Impact of Non-Simultaneous P/f and Q/V Grid Code Requirement...

引用

IEEE 6th international symposium on Power Electronics for Distributed generation Systems (PEDG)

作者： Lissandron, Stefano Sgarbossa, Riccardo Dalla Santa, Luca Mattavelli, Paolo Turri, Roberto Cerretti, Alberto Univ Padua Dept Informat Engn I-35100 Padua Italy Univ Padua Dept Management & Engn I-35100 Padua Italy Univ Padua Dept Ind Engn I-35100 Padua Italy ENEL SpA Div Infrastrutture & Reti Ingn & Unificaz Rome Italy

ISBN: (纸本)9781479985869

the analysis of unintentional islanding in distribution grids with a large penetration of renewable energy sources is of increasing interest due to the recently introduced requirements of P/f and Q/V supporting capabilities of Distributed Energy Resources (DERs) and the wider frequency and voltage ranges, DERs should be able to operate with, before protection tripping. DER anti-islanding protections, if present, may fail to detect this grid transition and so uncontrolled islanding operation may appear. Since this operating mode may be dangerous for the electric network operation and may cause damages for the grid equipment, in this paper the increase of its risk due to P/f and Q/V droop characteristics of generators is addressed. Analytic results are initially derived for the steady-state unintentional islanding operation and then they are validated on a laboratory-scale grid setup. the proposed investigation will show that the risk of permanent unintentional islanding increases introducing P/f or Q/V droop regulation and that such risk is maximum including both the P/f and Q/V droop regulations, rather than only one of them.

关键词： QV Power grids Network operations Density estimation robust algorithm Trellis codes Renewable energy renewable energy sources

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Automatic generation of VHDL hardware code from data flow graphs

Automatic generation of VHDL hardware code from data flow gr...

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6th IEEE international symposium on Applied Computational Intelligence and Informatics, SACI 2011

作者： Necsulescu, Philip I. Groza, Voicu University of Ottawa School of Information Technology and Engineering Ottawa Canada

ISBN: (纸本)9781424491094

the Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. the framework and algorithms to generate the hardware from an Intermediate Representation (IR) of the C code is needed. this paper presents the conceiving, design, and development of a module that generates the hardware for custom instructions identified by specialized SHIRA components without the need for any user interaction. the module is programmed in Java and takes a Data Flow Graph (DFG) as an IR for input. It then generates VHDL code that targets the Altera Field Programmable Gate Arrays (FPGA). It is possible to use separate components for each operation or to set a maximum number for each component which leads to component reuse and reduces chip area use. the performance improvement of the generated code is compared to using only the processor's standard instruction set. © 2011 IEEE.

关键词： Data flow graphs

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Building code Generators for DSLs Using a Partial Evaluator for the Xtend Language 6

Building Code Generators for DSLs Using a Partial Evaluator ...

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6th international symposium on Leveraging Applications of Formal Methods, Verification and Validation (ISoLA)

作者： Birken, Klaus Itemis AG Stuttgart Germany

ISBN: (纸本)9783662452349;9783662452332

For several years now, domain-specific languages (DSLs) are a mainstream tool for establishing model-based development environments in real-world projects. Typical back-end tools for external DSLs are interpreters and code generators. Partial evaluation is a well-known technique for program specialization, with the use case of specializing interpreters to target programs. However, the automatic generation of code generators from a DSL's interpreter is by no means ubiquitous in industrial DSL projects. In this paper, we show how interpreters for a DSL can be used as a basis for automatic generation of efficient target code. this is possible by implementing a partial evaluator for the mainstream DSL toolset Xtext/Xtend.

关键词： partial evaluation program specialization interpreters code generation domain-specific languages Xtext Xtend

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Amorphous carbon process optimization to increase hard mask and lithographic capabilities by its step coverage improvement 6

Amorphous carbon process optimization to increase hard mask ...

引用

6th international symposium on Next generation Electronics, ISNE 2017

作者： Lai, Chun Chi Hsing Chang, Yueh Ju Chien, Hung Chen Lu, Ming Powerchip Technology Corporation No. 12 Li-Hsin 1st Rd. Hsinchu Science Park Hsinchu Taiwan

ISBN: (纸本)9781538630969

the capabilities of hard mask (HM) and lithographic are strongly depended on the step coverage (S/C) of HM. Using C2H2 base amorphous carbon (a-C) as HM gets better sidewall S/C than using C3H6 one due to superior sticking coefficient (higher C/H ratio). As to performance of against PR rework, overlay mark without damage is displayed by adopting C2H2 base a-C even five times PR rework. In our case, bad sidewall S/C of a-C film induces the device pattern damage of micro control unit (MCU). After optimizing the process of C2H2 base a-C based on DOE trend of process parameter, sidewall S/C marvelously increases from 49% to 91%. therefore, the amount of device pattern damage of MCU is obviously reduced. © 2017 IEEE.

关键词： Amorphous carbon

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Source code Summarization & Comment generation with NLP: A New Index Proposal 6

Source Code Summarization & Comment Generation with NLP: A N...

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6th international Congress on Human-Computer Interaction, optimization and Robotic Applications, HORA 2024

作者： Kilic, M. Alp Eren Adak, M. Fatih Computer Engineering Department Sakarya University Sakarya Turkey

ISBN: (纸本)9798350394634

Understanding and maintaining source code is a critical aspect of software development. Source code comments play a crucial role to increase understandability and sustainability. However, creating and maintaining comprehensive comments alongside the source code can be labour intensive and lead to inconsistencies. this study investigates the effectiveness of Natural Language Processing (NLP) techniques in automating the source code summarization and comment generation processes to alleviate these challenges. We propose a novel evaluation framework that assesses the sufficiency and quality of generated comments in aiding source code comprehension. Leveraging state-of-the-art NLP models, our approach aims to summarize source code functionalities and generate descriptive comments automatically. Furthermore, we introduce a new index proposal tailored to evaluate the adequacy of generated comments in capturing the essence of source code. Software projects with a high Cyclomatic Complexity value need to be explained and well documented as they are projects with high complexity. In this study, different popular repositories were analysed and comments were generated for uncommented functions using natural language processing approaches. With the proposed index, both Cyclomatic Complexity value and productivity were evaluated. the successful results obtained from this study shows that automatic comment generation approaches can be used much more successfully in the near future. © 2024 IEEE.

关键词： Deep learning

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