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检索条件"任意字段=6th International Symposium on Parallel Architectures, Algorithms, and Programming, PAAP 2014"

共 22 条记录，以下是11-20 订阅

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Performance Characterization and Evaluation of HPC algorithms on Dissimilar Multicore architectures 16

Performance Characterization and Evaluation of HPC Algorithm...

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16th IEEE international Conference on High Performance Computing and Communications HPCC 2014\11th IEEE international Conference on Embedded Software and Systems ICESS 2014\6th international symposium on Cyberspace Safety and Security CSS 2014

作者： Krishnan, S. P. T. Veeravalli, Bharadwaj Agcy Sci Technol & Res Inst Infocomm Res Singapore 138632 Singapore Natl Univ Singapore Dept Elect & Comp Engn Singapore 117583 Singapore

ISBN: (纸本)9781479961238

In this paper, we share our experiences in using two important yet different High Performance Computing (HPC) architectures for evaluating two HPC algorithms. the first architecture is an Intel x64 ISA based homogenous multicore with Uniform Memory Access (UMA) type shared-memory based Symmetric Multi-Processing system. the second architecture is an IBM Power ISA based heterogenous multicore with Non-Uniform Memory Access (NUMA) based distributed-memory Asymmetric Multi-Processing system. the two HPC algorithms are for predicting biological molecular structures, specifically the RNA secondary structures. the first algorithm that we created is a parallelized version of a popular serial RNA secondary structure prediction algorithm called PKNOTS. the second algorithm is a new parallel-by-design algorithm that we have developed called MARSs. Using real Ribo-Nucleic Acid (RNA) sequences, we conducted large-scale experiments involving hundreds of sequences using the above two algorithms. Based on thousands of data points that we collected as an outcome of our experiments, we report on the observed performance metrics for both the algorithms on the two architectures. through our experiments, we infer that architectures with specialized co-processors for number-crunching along with high-speed memory bus and dedicated bus controllers generally perform better than general-purpose multi-processor architectures. In addition, we observed that algorithms that are intrinsically parallelized by design are able to scale & perform better by taking advantage of the underlying parallel architecture. We further share best practices on handling scalability aspects with regards to workload size. We believe our results are applicable to other HPC applications on similar HPC architectures.

关键词： ARCHITECTURE High Performance Computing algorithms Multi-core processors Prediction algorithms parallel architectures Multi-Processing Performance metrics Building construction Best Practices

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parallel Aligning Multiple Metabolic Pathways on Hybrid CPU and GPU architectures 8th

Parallel Aligning Multiple Metabolic Pathways on Hybrid CPU ...

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8th international symposium on parallel architectures, algorithms, and programming (paap)

作者： Huang, Yiran Zhong, Cheng Zhang, Jinxiong Li, Ye Liu, Jun Guangxi Univ Sch Comp & Elect & Informat Nanning Peoples R China Guangxi Univ Key Lab Parallel & Distributed Comp Nanning Peoples R China Shenzhen Key Lab Serv Comp & Applicat Guangdong Key Lab Popular High Performance Comp Shenzhen Peoples R China Guangxi Teachers Educ Univ Data Sci Guangxi Higher Educ Key Lab Nanning Peoples R China

ISBN: (纸本)9789811064425;9789811064418

Metabolic pathway alignment remains an important tool in systems biology, and has become even more important with the growing mass of metabolic pathway data. However, the process of aligning multiple metabolic pathways scale poorly with either the number of pathways or with the size of pathways, and no attempts have been made to exploit the parallelism of the pathway alignments to improve the efficiency. this paper proposes a parallel metabolic pathway alignment method called PMMPA. In PMMPA, we design a commonly used parallel algorithm for the computation of reaction (node) similarity in GPU, and implement a parallel strategy for aligning multiple metabolic pathways in multi-core CPU. the experimental results show that this parallel alignment implementation achieves at most 300 times faster than the single-threaded version, the parallel implementation of aligning metabolic pathways on the hybrid CPU and GPU architecture is promising in improving the efficiency.

关键词： Metabolic pathway alignment Reaction similarity CPU and GPU computing Phylogenetic tree

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An Integrated Hardware-Software Approach to Task Graph Management 16

An Integrated Hardware-Software Approach to Task Graph Manag...

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作者： Engelhardt, Nina Dallou, Tamer Elhossini, Ahmed Juurlink, Ben Tech Univ Berlin Embedded Syst Architecture Einsteinufer 17 D-10587 Berlin Germany

ISBN: (纸本)9781479961238

Task-based parallel programming models with explicit data dependencies, such as OmpSs, are gaining popularity, due to the ease of describing parallel algorithms with complex and irregular dependency patterns. these advantages, however, come at a steep cost of runtime overhead incurred by dynamic dependency resolution. Hardware support for task management has been proposed in previous work as a possible solution. We present VSs, a runtime library for the OmpSs programming model that integrates the Nexus++ hardware task manager, and evaluate the performance of the VSs-Nexus++ system. Experimental results show that applications with fine-grain tasks can achieve speedups of up to 3.4x, while applications optimized for current runtimes attain 1.3x. Providing support for hardware task managers in runtime libraries is therefore a viable approach to improve the performance of OmpSs applications.

关键词： OmpSs parallel programming models task dataflow hardware task scheduler runtime library

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Task-Based parallelization of Unstructured Meshes Assembly using D&C Strategy 16

Task-Based Parallelization of Unstructured Meshes Assembly u...

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作者： Petit, Eric thebault, Loic Moller, Nathalie Jalby, William Dinh, Quang Univ Versailles UVSQ CNRS PRISM Versailles France Dassault Aviat St Cloud France

ISBN: (纸本)9781479961238

this paper introduces our work on parallelizing unstructured mesh applications in shared memory. Our approach uses task-based runtime and Divide and Conquer recursive bissection strategy for the work decomposition. We demonstrate this parallelization strategy on the unstructured mesh assembly step of an industrial CFD application. Preliminary results show a speedup of 1.8x on a 12 cores node and a performance on Xeon Phi equivalent to 15 Ivy Bridge cores, with a parallel efficiency higher than 90% on the physical cores.

关键词： parallel programming parallel algorithms Multithreading

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Implementing parallel genetic algorithm using concurrent-functional languages 6

Implementing parallel genetic algorithm using concurrent-fun...

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6th international Conference on Evolutionary Computation theory and Applications, ECTA 2014, Part of the 6th international Joint Conference on Computational Intelligence, IJCCI 2014

作者： Albert-Cruz, J. Merelo, J.J. Acevedo-Martínez, L. De Las Cuevas, Paloma Centro de Estudios de Matemática Computacional Universidad de Ciencias Informáticas La Habana Cuba Dept. Arquitectura y Tecnología de los Computadores Universidad de Granada Granada Spain

ISBN: (纸本)9789897580529

the spread of multiprocessor and multi-core architectures have a pervasive effect on the way software is developed. In order to take full advantage of them, a parallel implementation of every single program would be needed, but also a radical reformulation of the algorithms that are more appropriate to that kind of implementation. In this work we design and implement an evolutionary computation model using programming languages with built-in concurrent concepts. this article shows the advantages of these paradigms in order to implement a parallel genetic algorithm (pGA) with an island pools based topology in the concurrent-functional oriented programming languages: Erlang, Scala, and Clojure. Some implementation decisions are analyzed and the results of the solution of a study case are shown.

关键词： Genetic algorithms

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FLLOP: A Massively parallel Solver Combining FETI Domain Decomposition Method and Quadratic programming 16

FLLOP: A Massively Parallel Solver Combining FETI Domain Dec...

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16th IEEE Int Conf on High Performance Computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Hapla, Vaclav Cermak, Martin Markopoulos, Alexandros Horak, David VSB Tech Univ Ostrava Dept Appl Math Ostrava 70833 Czech Republic VSB Tech Univ Ostrava Dept Mech Mat Ostrava 70833 Czech Republic VSB Tech Univ Ostrava Natl Supercomp Ctr IT4Innovat 17 Listopadu 15-2172 Ostrava 70833 Czech Republic

ISBN: (纸本)9781479961238

FLLOP (FETI Light Layer On top of PETSc) is a novel solver for linear systems and more general quadratic programming problems. It connects quadratic programming algorithms with FETI domain decomposition methods that bring high parallel scalability and at the same time high accuracy and robustness needed in engineering applications. According to its name, FLLOP forms an extension of the renowned PETSc software framework for parallel numerical solution of partial differential equations. It can be thus adopted by PETSc users with relative ease. the above-mentioned facts makes FLLOP a unique project. It now forms a solver part of our emerging PERMON toolbox for parallel, Efficient, Robust, Modular, Object-oriented, Numerical simulations. We introduce one more PERMON tool, PermonCube, which serves as a benchmark generation tool for FLLOP in massively parallel environment.

关键词： FETI FLLOP PERMON PETSc Permon Cube domain decomposition method quadratic programming quadratic programming Fetus Solvers parallel Lines

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Prototyping N-body simulation in Proteus

Prototyping N-body simulation in Proteus

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Proceedings of the 6th international parallel Processing symposium

作者： Mills, Peter H. Nyland, Lars S. Prins, Jan F. Reif, John H. Duke Univ Durham United States

ISBN: (纸本)0818626720

this paper explores the use of Proteus, an architecture-independent language suitable for prototyping parallel and distributed programs. Proteus is a high-level imperative notation based on sets and sequences with a single construct for the parallel composition of processes communicating through shared memory. Several different parallel algorithms for N-body simulation are presented in Proteus, illustrating how Proteus provides a common foundation for expressing the various parallel programming models. this common foundation allows prototype parallel programs to be tested and evolved without the use of machine-specific languages. To transform prototypes to implementations on specific architectures, program refinement techniques are utilized. Refinement strategies are illustrated that target broad-spectrum parallel intermediate languages, and their viability is demonstrated by refining an N-body algorithm to data-parallel CVL code.

关键词： parallel processing systems

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Research on Mahalanobis Distance Algorithm Optimization Based on OpenCL 16

Research on Mahalanobis Distance Algorithm Optimization Base...

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16th IEEE Int Conf on High Performance Computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Xie, Qingchun Zhang, Yunquan Jia, Haipeng Lu, Yongquan Commun Univ China High Performance Comp Ctr Beijing 100024 Peoples R China Chinese Acad Sci Inst Software Lab Parallel Comp Beijing 100190 Peoples R China Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100190 Peoples R China

ISBN: (纸本)9781479961238

Mahalanobis distance algorithms has been widely used in machine learning and classification algorithms, and it has an important practical significance in improving the performance of some applications through GPU, especially in some applications with high real-time demand. However, due to the complexity of the GPU hardware architectures, how to complete the algorithm optimization and achieve high performance portability on different GPU platforms is still a hard work. the redundant calculation of traditional Mahalanobis distance algorithm is very large and is hard to implement parallel. In this paper, we not only throw light on the universal ways to properly map mature algorithms to GPU devices to implement the Mahalanobis distance, such as fixed number of workgroups and vectorization, but also put forward five valuable methods of performance optimization on heterogeneous computing platforms, such as two-dimension NDRange workgroup arrangement, Uberkernel, binary reduction with the help of LDS register in one workgroup. Furthermore, We also demonstrate the high performance of our implementation by comparing it with a well-optimized CPU version from OpenCV library. Experimental results show that speedup reaches up 10.59 times on NVIDIA GPU C2050, 8.55 times on AMD HD5850 and 16.08 times on HD7970. the last experimental results verified the effectiveness of optimization methods which we proposed.

关键词： OpenCL Heterogeneous Computing GPU Mahalanobis parallel Optimization

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Enabling PGAS Productivity with Hardware Support for Shared Address Mapping;a UPC Case Study 16

Enabling PGAS Productivity with Hardware Support for Shared ...

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16th IEEE Int Conf on High Performance Computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Serres, Olivier Kayi, Abdullah Anbar, Ahmad El-Ghazawi, Tarek George Washington Univ ECE Dept Washington DC 20052 USA Intel Hillsboro OR USA

ISBN: (纸本)9781479961238

the Partitioned Global Address Space (PGAS) programming model strikes a balance between the locality-aware, but explicit, message-passing model (e.g. MPI) and the easy-to-use, but locality-agnostic, shared memory model (e.g. OpenMP). However, the PGAS rich memory model comes at a performance cost which can hinder its potential for scalability and performance. To contain this overhead and achieve full performance, compiler optimizations may not be sufficient and manual optimizations are typically added. this, however, can severely limit the productivity advantage. Such optimizations are usually targeted at reducing address translation overheads for shared data structures. this paper proposes a hardware architectural support for PGAS, which allows the processor to efficiently handle shared addresses. this eliminates the need for such hand-tuning, while maintaining the performance and productivity of PGAS languages. We propose to avail this hardware support to compilers by introducing new instructions to efficiently access and traverse the PGAS memory space. A prototype compiler is realized by extending the Berkeley Unified parallel C (UPC) compiler. It allows unmodified code to use the new instructions without the user intervention, thereby creating a real productive programming environment. Two different implementations of the system are realized: the first is implemented using the full system simulator Gem5, which allows the evaluation of the performance gain. the second is implemented using a softcore processor Leon3 on an FPGA to verify the implementability and to parameterize the cost of the new hardware and its instructions. the new instructions show promising results for the NAS parallel Benchmarks implemented in UPC. A speedup of up to 5.5x is demonstrated for unmodified codes. Unmodified code performance using this hardware was shown to also surpass the performance of manually optimized code by up to 10%.

关键词： parallel programming parallel architectures High Performance Computing

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A Lightweight Block Storage Security Scheme based on LT Coding for 6G Network

A Lightweight Block Storage Security Scheme based on LT Codi...

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international symposium on parallel architectures, algorithms and programming (paap)

作者： Hui Li Ruijin Zhou DongCong Shi Xuanhao Luo Xue Chen Dan Liao School of Information and Communication Engineering University of Electronic Science and Technology of China Chengdu China Facility of information engineering and automation Kunming University of Science and Technology Kunming China

ISBN: (纸本)9781665496407

the 6G is the space-terrestrial integrated network combining the Internet of things and satellite network. And the data security problem of 6G network has become a research hotpot. the introduction of blockchain technology in 6G network can effectively improve the safety of data storage. However, with the continuous addition of IoT nodes and satellite nodes, more and more data are stored in blocks, which makes the problems of large storage space and low storage efficiency prominent. therefore, for 6G network, this paper proposes a lightweight block storage security scheme based on LT coding. In the proposed storage scheme, satellite nodes are responsible for the complete storage of the blockchain. the blocks are encoded by using LT code and stored at the satellite nodes in the form of slices, while the latest blocks are stored in IoT nodes. this greatly reduces the storage burden of 6G network. To suit large-scale nodes of 6G network, the traditional blockchain indexing method has been improved. the IoT nodes can calculate the jump block number according to their own block number, thus realizing the jump indexing and verification of the block. Finally, the simulation results prove that the proposed storage scheme has superior performance in block recovery success rate and block storage occupancy.

关键词： 6G mobile communication Satellites Simulation Scalability programming Encoding Blockchains

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