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检索条件"任意字段=6th International Workshop on Embedded Computer Systems - Architectures, Modeling and Simulation"

共 361 条记录，以下是91-100 订阅

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On-chip dynamic programming networks using 3D-TSV integration

On-chip dynamic programming networks using 3D-TSV integratio...

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2011 11th international Conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Al-Dujaily, Ra'Ed Mak, Terrence Zhou, Kuan Lam, Kai-Pui Meng, Yicong Yakovlev, Alex Poon, Chi-Sang School of Electrical Electronic and Computer Engineering Newcastle University United Kingdom Department of Electrical and Electronic Engineering New Hampshire University United States Department of Systems Engineering Chinese University of Hong Kong Hong Kong Hong Kong Harvard-MIT Health Sciences and Technology Massachusetts Institute of Technology United States

ISBN: (纸本)9781457708008

Recent technological advances in three-dimensional (3D) semiconductor fabrication have provided a promising platform for realizing densely interconnected multicore, multiprocessor, and networks-on-chip (NoC) based systems. As the on-chip complexity grows significantly with the number of computational, control, and communication units, design considerations and the provision for efficient run-time resources management in large-scale system becomes critical. We have developed an on-chip distributed dynamic-programming (DP) network [3] [5] for a range of applications including optimal paths planning [6], dynamic routing [5] and deadlock detection [2]. this paper presents a design of DP-network, implemented in a fully stacked 3-layer three-dimensional (3D) through-silicon via (TSV) 150 nm CMOS technology through MIT Lincoln Lab [1]. the vertical inter-unit communication is achieved by means of TSV, and the mesh interconnection provides a natural minimal area overhead associated with this communication. the prototype circuit measures 2mm×2mm. Test results demonstrated the effectiveness of such a DP-network for deadlock detection and the computational delay is less than 9 ns for detecting deadlock from a large-scale network. this work provides promising results for future networks-on-chip application using 3D embedded DP-network. © 2011 IEEE.

关键词： Network-on-chip

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Design and Development of a CPU Scheduler Simulator for Educational Purposes Using SDL

Design and Development of a CPU Scheduler Simulator for Educ...

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6th international workshop on System Analysis and modeling - About Models (SAM)

作者： Rodriguez-Cayetano, Manuel Univ Valladolid Dept Signal Theory & Telemat Engn ES-47011 Valladolid Spain

ISBN: (纸本)9783642216510

this paper presents the design and development of a CPU scheduler simulator using SDL. this simulator enables us to study the behavior of one level and multilevel queue scheduling algorithms (including the real-time ones), and to obtain performance statistics for algorithm evaluation. In addition, a multi-platform graphical user interface, based on the Tcl/Tk language, has been developed to simplify the simulator use. the paper also presents our experiences in using SDL for the specification of CPU scheduling algorithms for educational purposes.

关键词： Operating systems CPU scheduling simulation GUI Tcl/Tk

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simulation Tools Enabling Research in Convergence of Fixed and Mobile Networks

Simulation Tools Enabling Research in Convergence of Fixed a...

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Int Joint Conference of 10th IEEE Int Conf on Trust, Security and Privacy in Computing and Communications (TrustCom) / 8th IEEE Int Conf on embedded Software and systems (ICESS) / 6th Int Conf on Frontier of computer Science and Technology (FCST)

作者： Bontozoglou, Andreas Yang, Kun Guild, Ken Univ Essex Sch Comp Sci & Elect Engn Colchester Essex England

ISBN: (纸本)9780769546001

the massive increase of mobile handsets in conjunction with the new and more demanding services deployed over wireless networks lead to huge bandwidth requirements for both the wireless and the backhaul networks. Ethernet Passive Optical Network deployment has already been started to replace E-1/T1 lines. In addition wireless broadband access is taking place mostly with the use of WiMax. Integration and convergence of the above technologies had been proven to have many benefits. Due to the nature and the complexity though of the scenarios in this area, a large scale simulator, supporting multiple services and QoS is needed in order to validate new network and resource management algorithms. In this paper a simulator developed using OMNet++ framework is presented. the designed modules and their functionality are listed. A discussion on how these could be used to form different convergence architectures and the major outcome/results of such a simulation are explained.

关键词： FMC OMNet plus Convergence simulator EPON WiMax 802.16 802.3ah 802.1q

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Dataflow programming model for reconfigurable computing

Dataflow programming model for reconfigurable computing

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international workshop on Reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： L. Gantel A. Khiar B. Miramond A. Benkhelifa F. Lemonnier L. Kessal ETIS Laboratory-UMR CNRS 8051 University of Cergy-Pontoise / ENSEA Cergy-Pontoise France Embedded System Laboratory Thales Research and Technology Limited Palaiseau France

this paper addresses the problem of image processing algorithms implementation onto dynamically and reconfigurable architectures. Today, these systems-on-Chip (SoC), offer the possibility to implement several heterogeneous processing elements in a single chip. It means several processors, few hardware accelerators as well as communication mediums between all these components. Applications for this kind of platform are described with software threads, running on processors, and specific hardware accelerators, running on hardware partitions. this paper focuses on the complex problem of communication management between software and hardware actors for dataflow oriented processing, and proposes solutions to leverage this issue.

关键词： Hardware Instruction sets Middleware Operating systems computer architecture Computational modeling

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Design methods of multithreaded architectures for multicore microcontrollers

Design methods of multithreaded architectures for multicore ...

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international Symposium on Applied Computational Intelligence and Informatics ( SACI)

作者： Horia V. Caprita Mircea Popa Computer Science and Automatic Control Department Lucian Blaga University of Sibiu Sibiu Romania Faculty of Automation and Computers Polytechnic University of Timisoara Timisoara Romania

the development of electronic technology today has allowed the implementation of complex architectures, which led to the emergence of multicore processors technology. Multicore architectures are built from superscalar and multithreaded processors. Integrating new technologies in embedded applications requires the development of multicore processors that can be integrated into a smaller area like a classic microcontroller. these processors must manage fewer resources and be able to manage multiple tasks simultaneously. In this paper we present a method of modeling, simulation and evaluation of two multithreaded architectures with limited resources, which could be integrated into embedded systems: Interleaved multithreading (IMT) and Blocked multithreading (BMT). Both techniques permit the processing of multiple independent threads, concurrently. In this paper we propose a SimpleScalar Interleaved Multithreading architecture (SS-IMT) and a SimpleScalar Blocked Multithreading architecture (SS-BMT) that are derived from SimpleScalar simulator. We will evaluate the performances of these architectures compared to the performance of standard SimpleScalar architecture.

关键词： Context Instruction sets computer architecture Registers Multithreading Benchmark testing

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Co-simulation of embedded systems in a heterogeneous MoC-based modeling framework

Co-simulation of embedded systems in a heterogeneous MoC-bas...

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international Symposium on Industrial embedded systems

作者： Seyed Hosein Attarzadeh Niaki Ingo Sander Electronic Systems School of Information and Communication Technology KTH Royal Institute of Technology Stockholm Sweden

New design methodologies and modeling frameworks are required to provide a solution for integrating legacy code and IP models in order to be accepted in the industry. To tackle this problem, we introduce the concept of wrappers in the context of a formal heterogeneous embedded system modeling framework. the formalism is based on the language-independent concept of models of computation. Wrappers enable the framework to co-simulate/co-execute with external models which might be legacy code, an IP block, or an implementation of a partially refined system. they are defined formally in order to keep the analyzability of the original framework and also enable automations such as generation of model wrappers and co-simulation interfaces. As a proof of concept, three wrappers for models in different abstraction levels are introduced and implemented for two case studies.

关键词： Computational modeling Adaptation models Synchronization Semantics embedded systems computer architecture Engines

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NoCmodel: An extensible framework for Network-on-Chips modeling

NoCmodel: An extensible framework for Network-on-Chips model...

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international workshop on Reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： Oscar Díaz Armando Astarloa Aitzol Zuloaga Jesús Lázaro Jaime Jimenez Department of Electronics and Telecommunications University of Basque Country (UPV-EHU) Spain

Network-on-Chips (NoC) is an emerging concept to address the growing complexity in digital electronics systems. However, current design methodology is based on traditional HDL languages written manually or with the help of code generation tools. In order to deal with NoC design and management we create NoCModel: an extensible framework for NoC modeling based on Python language, with support for simulation and code generation. this paper presents the motivation behind the build and use of this tool, the capabilities currently present in it, an explanation of the core and its add-ons and some results obtained from it.

关键词： Unified modeling language Hardware Routing computer architecture Algorithm design and analysis Load modeling Hardware design languages

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Self-organization of reconfigurable processing elements during mobile robots missions

Self-organization of reconfigurable processing elements duri...

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international workshop on Reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： Laurent Rodriguez Jerôme Fellus Benoît Miramond ETIS Laboratory UMR 8051 CNRS ENSEA UCP Cergy-Pontoise France

this paper describes a bio-inspired architectural approach to design highly adaptive systems in the context of mobile robotics. the concerned robots evolve in an indoor unknown environment and then exhibit several behaviours such as landscape learning, obstacle avoidance, path planning, sensori-motor control. We aim at designing the intelligent embedded controller of those robots. the controller will be able to self-organize its elements in order to adapt its architecture to the robot behaviour. We focus in this paper on the description of the neural network which was developed to self-organize the system. We present the simulation results of our method.

关键词： Robot sensing systems computer architecture Neurons Motion estimation Biological neural networks Self organizing feature maps

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Short-term stock price prediction using MLP in moving simulation mode

Short-term stock price prediction using MLP in moving simula...

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IEEE international workshop on Intelligent Data Acquisition and Advanced Computing systems: Technology and Applications

作者： Volodymyr Turchenko Patrizia Beraldi Francesco De Simone Lucio Grandinetti Research Institute of Intelligent Computer Systems Ternopil National Economic University Ternopil Ukraine Department of Electronics Informatics and Systems University of Calabria Rende Cosenza Italy

the features of a short-term prediction of a stock price using a multi-layer perceptron in a moving simulation application mode are considered in this paper. the input data for the short-term prediction mode are analyzed. the architecture of the predicting model is developed. the simulation modeling results show a high accuracy of the prediction on the historical stock prices of Fiat company.

关键词： Predictive models Artificial neural networks Training Data models Stock markets Testing Neurons

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An area-efficient 2-D convolution implementation on FPGA for space applications

An area-efficient 2-D convolution implementation on FPGA for...

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international Design and Test workshop

作者： Stefano Di Carlo Giulio Gambardella Marco Indaco Daniele Rolfo Gabriele Tiotto Paolo Prinetto Politecnico di Torino Dipartimento di Automatica e Informatica Torino Italy CINI Roma Italy

the 2-D Convolution is an algorithm widely used in image and video processing. Although its computation is simple, its implementation requires a high computational power and an intensive use of memory. Field Programmable Gate Arrays (FPGA) architectures were proposed to accelerate calculations of 2-D Convolution and the use of buffers implemented on FPGAs are used to avoid direct memory access. In this paper we present an implementation of the 2-D Convolution algorithm on a FPGA architecture designed to support this operation in space applications. this proposed solution dramatically decreases the area needed keeping good performance, making it appropriate for embedded systems in critical space applications.

关键词： Field programmable gate arrays computer architecture Kernel Image processing Convolvers Bandwidth

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