embedded Sensor Networks are deeply immersed in their environment, and are difficult to protect from abuse or theft. Yet the software contained within these remote sensors often represents years of development, and re...
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ISBN:
(纸本)9783540705499
embedded Sensor Networks are deeply immersed in their environment, and are difficult to protect from abuse or theft. Yet the software contained within these remote sensors often represents years of development, and requires adequate protection. We present a software based solution for the Texas Instruments C5509A DSP processor which uses object-code encryption and public-key key exchange with a server. the scheme is tightly integrated into the tool flow of the DSP processor and compatible with existing embedded processor design flows. We present performance and overhead metrics of the encryption algorithms and the security protocols. We also describe the limitations of the solution that originate from its software-only, backwards-compatible nature.
Array-OL specification model is a mixed graphical-textual language designed to model multidimensional intensive signal processing applications. Data and task parallelism are specified directly in the model. High level...
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ISBN:
(纸本)9783540705499
Array-OL specification model is a mixed graphical-textual language designed to model multidimensional intensive signal processing applications. Data and task parallelism are specified directly in the model. High level transformations are defined on this model, allowing the refactoring of an application and furthermore providing directions for optimization. the resemblances between withthe wide-known and used Loop trartsformations lead us to try taking concepts and results from this domain and see how they fit in Array-OL context.
the proceedings contain 37 papers. the topics discussed include: designing fault-tolerant component based applications with a model driven approach;model based synthesis of embedded software;formal specification of ga...
ISBN:
(纸本)3540877843
the proceedings contain 37 papers. the topics discussed include: designing fault-tolerant component based applications with a model driven approach;model based synthesis of embedded software;formal specification of gateways in integrated architectures;model-integrated development of cyber-physical systems;towards a middleware approach for a self-configurable automotive embedded system;context-aware middleware for reliable multi-hop multi-path connectivity;guiding organic management in a service-oriented real-time middleware architecture;self-describing and data propagation model for data distribution service;an ontology supported meta-interface for the development and installation of customized Web based telemedicine systems;and leveraging GIS technologies for Web-based smart places services.
Tomorrow's embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption constraint. In this context, the register file is ...
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ISBN:
(纸本)3540390944
Tomorrow's embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption constraint. In this context, the register file is one of the key sources of power consumption and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new approach to reduce the energy of the shared register file in upcoming embedded VLIW architectures with several processing units. Energy savings up to a 60% can be obtained in the register file without any performance penalty. It is based on a set of hardware extensions and a compiler-based energy-aware register assignment algorithm that enable the de/activation of parts of the register file (i.e. sub-banks) in an independent way at run-time, which can be easily included in these embeddedarchitectures.
Consumer electronics and communications products typically comprise embeddedsystems whose complexity dwarfs the supercomputer center of two decades ago. Along withthis embedded hardware capability have come equally ...
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this paper focuses on reducing computing time in large simulation models by replacing some of their elements with analytically determined solutions. In particular, we study realistic analytical server models that incl...
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this paper focuses on reducing computing time in large simulation models by replacing some of their elements with analytically determined solutions. In particular, we study realistic analytical server models that include operating system overhead. this overhead will be determined by measuring the behaviour of a representative workload. In this work, we propose a methodology to reduce the number of measurements based on information provided by an analytical workload model. the calibration of the model is also presented. As workload, the TPC-C benchmark was chosen due to our interest in transactional systems.
For the current generation of heterogeneous multi-core embedded processor, Systemon-Chip and FPGA platforms, implementation and optimisation of Digital Signal and Image Processing applications is an exceptionally chal...
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this paper describes extensions to VHDL to support system-level behavioral modeling by providing more abstract forms of communication and concurrency than those currently in the language. the report summarizes design ...
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this paper describes extensions to VHDL to support system-level behavioral modeling by providing more abstract forms of communication and concurrency than those currently in the language. the report summarizes design objectives and issues that must be considered in developing such extensions, and presents definitions of our extensions. the extensions for communication consist of channel types, channel objects, dynamically allocated channels, and message passing statements. the extensions for concurrency consist of process declarations and static and dynamic process instantiation statements. Use of the extensions is illustrated with examples.
the heterogeneity of modern MPSoC architectures, coupled withthe increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid performance model-ing techniques. Here, the ...
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ISBN:
(纸本)9781605584706
the heterogeneity of modern MPSoC architectures, coupled withthe increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid performance model-ing techniques. Here, the idea is to apply different modeling and analysis techniques to different subsystems/components of an ar-chitecture/application. Such hybrid techniques often turn out to be more efficient and accurate compared to relying on a single analy-sis technique for the entire system. However, the challenge asso-ciated withthis approach is to combine the different analysis re-sults effectively to obtain conservative performance estimates for the entire system. In this paper we study a hybrid scheme where certain system components are simulated (e.g. using instruction set simulators), whereas others are analyzed using a formal tech-nique called Real-Time Calculus (RTC). the main novelty of our approach stems from our use of this hybrid technique even for mul-tiple tasks mapped onto a single processing element. In contrast to this, previous approaches relied on either full simulation or RTC-based analysis for an entire architectural component (e.g. a proces-sor or a bus). the techniques we develop in this paper therefore al-low for both intra- and inter-processor hybrid performance model-ing and show how the different analysis results can be combined to efficiently obtain tight performance estimates for complex MPSoC architectures. We demonstrate the usefulness of this approach us-ing an MPEG-2 decoder application that is partitioned and mapped onto two processing elements connected by FIFO buffers. Copyright 2008 ACM.
Configuration management in distributed real-time systems and applications is considered. In particular, an idea for specifying the SW and HW architectures and modelingthe dynamical behaviour of embedded real-time ap...
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