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embedded Neural Network to Model-based Permanent Magnet Synchronous Motor Diagnostics

Embedded Neural Network to Model-based Permanent Magnet Sync...

第六届IEEE国际电力电子与运动控制会议 (2009 IEEE 6th international Power Electronics and Motion Control Conference-ECCE Asia

作者： Junhong Zhang Yunping Zou Youping Fan Huazhong Univ.of Science and Technology/College of Electrical & Electronics Engineering Wuhan430074 Huazhong Univ.of Science and Technology/College of Electrical & Electronics Engineering Wuhan430074 Wuhan Univ./College of Electrical Engineering Inst.of Bulk Grid SecurityWuhan430072China

Effective Fault detection and diagnosis (FDD) is especially important for some special applications, such as Navy ships operating in hostile environments. So far, FDD for nonlinear systems has not been fully explored. this paper makes an effort to fill the gap by extending an existing Monitor architecture and a series of algorithms for FDD of Permanent Magnet Synchronous Motors (PMSM). A fault model is proposed for the stator winding turn-to-turn fault of PMSM. the model provides a good compromise between computational complexity and model accuracy and is versatile for both the healthy and the fault condition. simulation studies demonstrate a good correspondence with both the theoretical analysis and the experimental observations in the paper.

关键词： Neural networks Permanent magnet motors Computational modeling Fault detection Fault diagnosis Marine vehicles Nonlinear systems computer architecture Stator windings Computational complexity

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Calibration of abstract performance models for system-level design space exploration

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JOURNAL OF SIGNAL PROCESSING systems FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第2期50卷 99-114页

作者： Pimentel, Andy D. thompson, Mark Polstra, Simon Erbas, Cagkan Univ Amsterdam Inst Informat Comp Syst Architecture Grp NL-1098 SJ Amsterdam Netherlands

High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such high-level modeling and simulation methods is that they should yield trustworthy performance estimations. this requires validation ( if possible) and calibration of the simulation models, which are two aspects that have not yet been widely addressed in the system-level community. this article presents a number of mechanisms for both calibrating isolated model components as well as a system-level performance model as a whole. We discuss these model calibration mechanisms in the context of our Sesame system-level simulation framework. Two illustrative case studies will also be presented to indicate the merits of model calibration.

关键词： system-level modeling and simulation performance analysis model calibration

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Accurate and scalable simulation of network of heterogeneous sensor devices

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JOURNAL OF SIGNAL PROCESSING systems FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第2期50卷 115-136页

作者： Wen, Ye Gurun, Selim Chohan, Navraj Wolski, Rich Krintz, Chandra Univ Calif Santa Barbara Santa Barbara CA 93106 USA

simulation is an important tool to study and analyze sensor networks. Prior work in sensor network simulation focuses on homogeneous devices. In this paper, we present a system that performs scalable and accurate simulation of a network of heterogeneous sensor devices, including both Stargate intermediate level devices and mote devices. We study accuracy, performance, and scalability of our system. the results show that we can achieve accurate functional behavior for both standalone Stargate simulation and ensemble simulation of a Stargate and motes. For motes, we have less than 4.06% cycle count error for all benchmarks and for Stargate, we have less than 10% error for most benchmarks, and less than 12.5% error for all benchmarks. We also achieve less than 3.6% error for all benchmarks when simulating an ensemble of Stargate and motes. Our system is also more scalable than prior work. We can simulate 160 sensor nodes in real time speed and 2,048 sensor nodes with ten times slowdown on a 16-node cluster.

关键词： simulation sensor network intermediate sensor node scalability

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Scenario selection and prediction for DVS-aware scheduling of multimedia applications

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JOURNAL OF SIGNAL PROCESSING systems FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第2期50卷 137-161页

作者： Gheorghita, S. V. Basten, T. Corporaal, H. Eindhoven Univ Technol Elect Syst Grp Dept Elect Engn NL-5600 MB Eindhoven Netherlands

Modern multimedia applications usually have real-time constraints and they are implemented using application-domain specific embedded processors. Dimensioning a system requires accurate estimations of resources needed by the applications. Overestimation leads to over-dimensioning. For a good resource estimation, all the cases in which an application can run must be considered. To avoid an explosion in the number of different cases, those that are similar with respect to required resources are combined into, so called application scenarios. this paper presents a methodology and a tool that can automatically detect the most important variables from an application and use them to select and dynamically predict scenarios, with respect to the necessary time budget, for soft real-time multimedia applications. the tool was tested for three multimedia applications. Using a proactive scenario-based dynamic voltage scheduler based on the scenarios and the runtime predictor generated by our tool, the energy consumption decreases with up to 19%, while guaranteeing a frame deadline miss ratio close to zero.

关键词： dynamic voltage scheduling soft real-time application scenarios embedded systems

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Memory-constrained block processing for DSP software optimization

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JOURNAL OF SIGNAL PROCESSING systems FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第2期50卷 163-177页

作者： Ko, Ming-Yung Shen, Chung-Ching Bhattacharyya, Shuvra S. Sandbridge Technol Inc White Plains NY USA Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA

Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into account this form of processing when implementing embedded software for DSP systems. Task-level vectorization, or block processing, is a useful dataflow graph transformation that can significantly improve execution performance by allowing subsequences of data items to be processed through individual task invocations. In this way, several benefits can be obtained, including reduced context switch overhead, increased memory locality, improved utilization of processor pipelines, and use of more efficient DSP oriented addressing modes. On the other hand, block processing generally results in increased memory requirements since it effectively increases the sizes of the input and output values associated with processing tasks. In this paper, we investigate the memory-performance trade-off associated with block processing. We develop novel block processing algorithms that carefully take into account memory constraints to achieve efficient block processing configurations within given memory space limitations. Our experimental results indicate that these methods derive optimal memory-constrained block processing solutions most of the time. We demonstrate the advantages of our block processing techniques on practical kernel functions and applications in the DSP domain.

关键词： block processing dataflow embedded systems vectorization block diagram compiler activation overhead context switch memory management

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Streaming systems in FPGAs

Streaming systems in FPGAs

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8th SAMOS international workshop

作者： Neuendorffer, Stephen Vissers, Kees Xilinx Res Labs San Jose CA 95119 USA

ISBN: (纸本)9783540705499

As FPGA devices have become larger and more capable, they have transitioned from being used primarily as flexible glue logic to being used as central data processing elements in many digital systems. Typically, these systems (including video processing, wired and wireless networking) rely on streaming architectures. these architectures differ significantly from traditional processor architectures and are able to offer unique challenges and benefits for system designers. In particular, streaming architectures in FPGAs are well suited for implementing upcoming digital convergence applications. We summarize how streaming architectures in FPGAs relate to other programmable platforms for embedded applications and focus on key problem areas related to the design tools and platform infrastructure that will drive these new applications.

关键词： dataflow FPGAs digital convergence

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Performance and energy consumption improvements in microprocessor systems utilizing a coprocessor data-path

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JOURNAL OF SIGNAL PROCESSING systems FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第2期50卷 179-200页

作者： Galanis, Michalis D. Dimitroulakos, Gregory Goutis, Costas E. Univ Patras ECE Dept VLSI Design Lab Patras 26500 Achaia Greece

the speedups and the energy reductions achieved in a generic single-chip microprocessor system by employing a high-performance data-path are presented. the data-path acts as a coprocessor that accelerates computational intensive kernel sections thereby increasing the overall performance. the authors have previously introduced the data-path which is composed by flexible computational components (FCCs). these components can realize any two-level sequence of primitive operations. the automated coprocessor synthesis method from high-level software description and its integration to a design flow for executing applications on the system is presented. the overall application speedups of eleven real-life applications, relative to the software execution on the microprocessor, are estimated using the design flow. these speedups are close to theoretical bounds and range from 1.78 to 5.84, having an average value of 3.04, while the overhead in circuit area is small. the energy savings range from 41 to 74%, while the reduction in the application energy-delay product has an average value of 80%. A comparison with another high-performance data-path showed that the proposed coprocessor achieves better performance, consumes less energy and has smaller area-time products for the generated data-paths. Additionally, the FCC data-path achieves better performance in accelerating kernels relative to a VLIW DSP core.

关键词： performance improvements energy reductions coprocessor data-path architectural synthesis design flow template units kernels

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Analysis of User Perceived QoS in Ubiquitous UMTS Environments Subject to Faults

Analysis of User Perceived QoS in Ubiquitous UMTS Environmen...

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6th international workshop on Software Technologies for embedded and Ubiquitous systems

作者： Bondavalli, Andrea Lollini, Paolo Montecchi, Leonardo Univ Florence Dipartimento Sistemi & Informat I-50134 Florence Italy

ISBN: (纸本)9783540877844

this paper provides a QoS analysis of a dynamic, ubiquitous UNITS network scenario in the automotive context identified in the ongoing EC HIDENETS project. the scenario comprises different types of mobile users, applications, traffic conditions, and outage events reducing the available network resources. Adopting a compositional modeling approach based on Stochastic Activity Networks formalism, we analyze the Quality of Service (QoS) both from the users' perspective and from the mobile operator's one. the classical QoS analysis is enhanced by taking into account the congestion both caused by the outage events and by the varying traffic conditions.

关键词： QoS analysis UMTS networks partial outages compositional modeling stochastic activity networks simulation

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embedded software architecture for diagnosing network and node failures in Wireless Sensor Networks

Embedded software architecture for diagnosing network and no...

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8th SAMOS international workshop

作者： Suhonen, Jukka Kohvakka, Mikko Hannikainen, Marko Hamalainen, Timo D. Tampere Univ Technol Dept Comp Syst FI-33101 Tampere Finland

ISBN: (纸本)9783540705499

Wireless Sensor Networks (WSNs) consist of embedded and distributed sensor nodes that operate on harsh operating conditions and with limited energy resources. To ensure the desired level of service, it is essential to detect and correct occurring network and node problems. In this paper, we propose a diagnostics software architecture for WSNs consisting of self-diagnostics on embedded sensor nodes and management tools for network analysis. We define a minimum set of diagnostics information that needs to be collected for analyzing the network errors and performance. To minimize communication overhead, collected information is categorized and only needed categories are requested from nodes. the diagnostics architecture is verified with a practical WSN implementation.

关键词： Sensor nodes

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Intellectual property protection for embedded sensor nodes

Intellectual property protection for embedded sensor nodes

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8th SAMOS international workshop

作者： Gora, Michael Simpson, Eric Schaumont, Patrick Virginia Polytech Inst & State Univ Secure Ernbedded Syst Grp Blacksburg VA 24061 USA

ISBN: (纸本)9783540705499

embedded Sensor Networks are deeply immersed in their environment, and are difficult to protect from abuse or theft. Yet the software contained within these remote sensors often represents years of development, and requires adequate protection. We present a software based solution for the Texas Instruments C5509A DSP processor which uses object-code encryption and public-key key exchange with a server. the scheme is tightly integrated into the tool flow of the DSP processor and compatible with existing embedded processor design flows. We present performance and overhead metrics of the encryption algorithms and the security protocols. We also describe the limitations of the solution that originate from its software-only, backwards-compatible nature.

关键词： Sensor nodes

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