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检索条件"任意字段=6th International Workshop on Embedded Computer Systems - Architectures, Modeling and Simulation"

共 376 条记录，以下是151-160 订阅

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ACM international Conference Proceeding Series

ACM International Conference Proceeding Series

引用

7th workshop on Parallel Programming and Run-Time Management Techniques for Many-Core architectures and 5th workshop on Design Tools and architectures For Multicore embedded Computing Platforms, PARMA-DITAM 2016

ISBN: (纸本)9781450340526

the proceedings contain 6 papers. the topics discussed include: stack size estimation on machine-independent intermediate code for OpenCL kernels;predictive modeling methodology for compiler phase-ordering;flexible resource allocation and management for application graphs on ReN MPSoC;low communication overhead dynamic mapping of multiple HEVC Video stream decoding on NOCs;deploying and monitoring hadoop MapReduce analytics on single-chip cloud computer;and runtime resource management for embedded and HPC systems.

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Towards multi-level-simulation using dynamic cloud environments 6

Towards multi-level-simulation using dynamic cloud environme...

引用

6th international Conference on simulation and modeling Methodologies, Technologies and Applications, SIMULTECH 2016

作者： Wittek, Stefan H.A. Göttsche, Michael Rausch, Andreas Grabowski, Jens Department of Informatics Clausthal University of Technology Clausthal-Zellerfeld Germany Institute of Computer Science Georg-August-University Göttingen Göttingen Germany

ISBN: (纸本)9789897581991

the engineering of cyber physical systems requires holistic simulation perspectives. To cope with the complexity of these systems, we aim to provide a simulation methodology that is efficient regarding model complexity. the required holistic perspective is reached on a coarse level, which is co-simulated with multiple detailed models of some areas of the system that are of particular interest to the investigated phenomena. Which areas are thus "zoomed in" is dynamic during a simulation run. To reflect this, the resulting Multi-Level-simulation is deployed in a dynamic cloud environment, using the provided hardware resources in a cost-efficient manner. © Copyright 2016 by SCITEPRESS - Science and Technology Publications, Lda. All rights reserved.

关键词： embedded systems

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embedded context aware hardware component generation for dataflow system exploration

引用

4th SAMOS international workshop

作者： McAllister, J Woods, R Walke, R Queens Univ Belfast Inst Elect Commun Informat Technol Belfast BT9 5AH Antrim North Ireland QinetiQ Ltd Real Time Embedded Syst Malvern WR14 3PS Worcs England

ISBN: (纸本)3540223770

Techniques for the rapid deployment and architectural exploration of complex digital signal processing algorithms on embedded processor platforms are gaining popularity. these become significantly more complicated when dedicated hardware components need to be integrated. the models on which such design methodologies and tools are based highlight the system level inflexibility with both pre-designed intellectual property cores and most customized component creation techniques. this paper presents a technique for overcoming these deficiencies using a dataflow model of computation, by allowing flexible circuit architectures to be created that can be optimized as desired, providing increased throughput with no extra resource usage in some situations.

关键词： Digital signal processing

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ASIP-eFPGA architecture for multioperable GNSS receivers

ASIP-eFPGA architecture for multioperable GNSS receivers

引用

8th SAMOS international workshop

作者： von Sydow, thorsten Blume, Holger Kappen, Goetz Noll, Tobias G. Univ Aachen Rhein Westfal TH Aachen Chair Elect Engn & Comp Syst D-52062 Aachen Germany

ISBN: (纸本)9783540705499

In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. the advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. the proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar CPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that;the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility.

关键词： ASIP arithmetic oriented eFPGA multioperable GNSS

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Design space exploration with automatic selection of SW and HW for embedded applications

引用

3rd international workshop on computer systems: architectures, modeling, and simulation, SAMOS 2003 and 4th international workshop on computer systems: architectures, modeling, and simulation, SAMOS 2004

作者： Mattos, Júlio C. B. Beck, Antônio C. S. Carro, Luigi Wagner, Flávio R. Federal University of Rio Grande do Sul Computer Science Institute Av. Bento Gonçalves Campus do Vale Porto Alegre9500 Brazil Federal University of Rio Grande do Sul Electrical Engineering Av. Oswaldo Aranha 103 Porto Alegre Brazil

ISBN: (纸本)3540223770

this paper presents a methodology for automatic selection of software and hardware IP components for embedded applications. Design space exploration is achieved by the correct selection of a SW-IP block to be executed in a platform containing different implementations of the same ISA. these different versions of the same ISA dissipate a different amount of power and require a different number of cycles to execute the same program. this way, by making the software execute on a different processor to achieve the required power or energy of an application, one can fine tune the platform for the desired market. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Application programs

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Flux caches: What are they and are they useful?

Flux caches: What are they and are they useful?

引用

5th international workshop on embedded computer systems: architectures, modeling, and simulation, SAMOS 2005

作者： Gaydadjiev, Georgi N. Vassiliadis, Stamatis Computer Engineering EEMCS TU Delft Netherlands

In this paper, we introduce the concept of flux caches envisioned to improve processor performance by dynamically changing the cache organization and implementation. Contrary to the traditional approaches, processors designed with flux caches instead of assuming a hardwired cache organization change their cache "design" on program demand. Consequently program (data and instruction) dynamic behavior determines the cache hardware design. Experimental results to confirm the flux caches potential are also presented. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Buffer storage

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Power modeling of Solid State Disk for Dynamic Power Management Policy Design in embedded systems

Power Modeling of Solid State Disk for Dynamic Power Managem...

引用

7th international workshop on Software Technologies for embedded and Ubiquitous systems

作者： Park, Jinha Yoo, Sungjoo Lee, Sunggu Park, Chanik Pohang Univ Sci & Technol POSTECH Dept Elect & Elect Engn 790-784 Hyoja Dong Pohang South Korea DS Solut Samsung Electron Memory Div Flash Software Team Hwasung South Korea

ISBN: (纸本)9783642102646

Power consumption now becomes the most critical performance limiting factor to solid state disk (SSD) in embedded systems. It is imperative to devise design methods and architectures for power efficient SSD designs. In our work, we present the first step towards low power SSD design, i.e., power estimation of SSD. We present a practical approach of SSD power estimation which tries to keep the advantage of real measurement, i.e., accuracy, while overcoming its limitations, i.e., long execution time and lack of repeatability (and high cost) by a trace-based simulation. Since it is based on real measurements, it takes into account the power consumption of SSD controller as well as that of Flash memories. We show the effectiveness of the presented method in designing a dynamic power management policy for SSD.

关键词： Solid state disk power consumption measurement trace-based simulation dynamic power management low power states

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A scalable embedded JPEG 2000 architecture

A scalable embedded JPEG 2000 architecture

引用

5th international workshop on embedded computer systems - architectures, modeling, and simulation

作者： Zhang, Chunhui Long, Yun Kurdahi, Fadi Univ Calif Irvine Dept EECS Irvine CA 92697 USA Intel Corp Mobile Wireless Commun Grp Santa Clara CA 95052 USA

ISBN: (纸本)354026969X

the latest image compression standard, JPEG 2000 is well tuned for diverse applications, thus raising various throughput demands on its building blocks. therefore, a JPEG 2000 encoder with the feature of scalability is favorable for its ability of meeting different throughput requirements. On the other hand, the large amounts of data streams underline the importance of bandwidth optimization in designing the encoder. the initial specification, especially in terms of loop organization and array indices, describes the data manipulations and, subsequently, influences the outcome of the architecture implementation. therefore, there is a clear need for the exploiting support, and we believe the emphasis should lie on the loop level steering. In this paper, we apply loop transformation techniques to a scalable embedded JPEG 2000 encoder design during the architectural exploration stage, considering not only the balance of throughput among different blocks, but also the reduction of data transfer. the architecture is prototyped onto Xilinx FPGA. (c) 2006 Elsevier B.V. All rights reserved.

关键词： JPEG 2000 VLSI image compressing architectural exploration embedded system

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Toward Integrated Virtual Execution Platform for Large-Scale Distributed embedded systems

Toward Integrated Virtual Execution Platform for Large-Scale...

引用

6th international workshop on Software Technologies for embedded and Ubiquitous systems

作者： Nakamoto, Yukikazu Abe, Issei Osaki, Tatsunori Terada, Hiroyuki Moriyama, Yu Univ Hyogo Grad Sch Appl Informat Chuo Ku 1-3-3 Higashi Kawasaki Cho Kobe Hyogo 6500044 Japan FUJITSU TEN Ltd Kobe Hyogo 6528510 Japan

ISBN: (纸本)9783540877844

the size and complexity of large-scale distributed embedded systems such as automotive and process control have increased recently. Sophisticated systems that are safe and environment friendly in the distributed systems require numerous types of sensor data, which are collected from various devices and sent to computers through networks. In order to develop the large-scale distributed embedded systems with high productivity and quality, a virtual execution environment platform is required. this platform integrates numerous CPU simulators and various device simulators through the network and provides network-wide simulation functionalities in the distributed system. In this paper, we present the requirements and initial system designs of a virtual execution environments platform for the development of the large-scale distributed embedded system software.

关键词： embedded systems

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Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation 08

Combination of instruction set simulation and abstract RTOS ...

引用

embedded systems Week 2008 - 6th IEEE/ACM/IFIP international Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

作者： Krause, Matthias Englert, Dominik Bringmann, Oliver Rosenstiel, Wolfgang FZI Forschungszentrum Informatik Haid-und-Neu-Str. 10-14 76131 Karlsruhe Germany Universität Tübingen Sand 13 72076 Tübingen Germany

ISBN: (纸本)9781605584706

Instruction set simulation and real time operating system modeling have become important issues for the design of distributed embedded systems. this paper presents a holistic approach to simulate a distributed, embedded system that includes target software, processing units, and abstract RTOS within a virtual prototype environment. the processing unit is modeled by an ISS, which is embedded in a SystemC environment to allow the integration into a platform model. In comparison to existing approaches, the RTOS is not directly running on the ISS but outsourced and replaced by an RTOS model. this step strongly reduces simulation time since the execution on the ISS is much more time consuming in contrast to the execution on the host processor. the results show the theoretical and measured performance gain depending on the RTOS scheduler and task switching. Copyright 2008 ACM.

关键词： embedded systems

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