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10th international workshop on Software and Compilers for embedded systems, SCOPES 2007

作者： Kupriyanov, Alexey Kissler, Dmitrij Hannig, Frank Teich, Jürgen Department of Computer Science 12 Hardware-Software-Co-Design University of Erlangen Nuremberg Germany

ISBN: (纸本)9781450378345

In this paper we present a new approach for generating high-speed optimized event-driven instruction set level simulators for adaptive massively parallel processor architectures. the simulator generator is part of a methodology for the systematic mapping, evaluation, and exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. the generation of high-speed cycle-accurate simulators is of utmost importance here, because they are directly used both for parallel processor architecture debugging and evaluation purposes, as well as during time-consuming architecture/compiler co-exploration. We developed a modeling environment which automatically generates a C++ simulation model either from a graphical input or directly from an XML-based architecture description. Here, we focus on the underlying event-driven simulation model and present our modeling environment, in particular the features of the graphical parallel processor architecture editor and the automatic instruction set level simulator generator. Finally, in a case-study, we demonstrate the pertinence of our approach by simulating different processor arrays. the superior performance of the generated simulators compared to existing simulators and simulator generation approaches is shown.

关键词： Parallel processing systems

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A scalable embedded JPEG 2000 architecture

A scalable embedded JPEG 2000 architecture

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5th international workshop on embedded computer systems - architectures, modeling, and simulation

作者： Zhang, Chunhui Long, Yun Kurdahi, Fadi Univ Calif Irvine Dept EECS Irvine CA 92697 USA Intel Corp Mobile Wireless Commun Grp Santa Clara CA 95052 USA

ISBN: (纸本)354026969X

the latest image compression standard, JPEG 2000 is well tuned for diverse applications, thus raising various throughput demands on its building blocks. therefore, a JPEG 2000 encoder with the feature of scalability is favorable for its ability of meeting different throughput requirements. On the other hand, the large amounts of data streams underline the importance of bandwidth optimization in designing the encoder. the initial specification, especially in terms of loop organization and array indices, describes the data manipulations and, subsequently, influences the outcome of the architecture implementation. therefore, there is a clear need for the exploiting support, and we believe the emphasis should lie on the loop level steering. In this paper, we apply loop transformation techniques to a scalable embedded JPEG 2000 encoder design during the architectural exploration stage, considering not only the balance of throughput among different blocks, but also the reduction of data transfer. the architecture is prototyped onto Xilinx FPGA. (c) 2006 Elsevier B.V. All rights reserved.

关键词： JPEG 2000 VLSI image compressing architectural exploration embedded system

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A model-driven automatically-retargetable debug tool for embedded systems

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7th international workshop on embedded computer systems: architectures, modeling, and simulation, SAMOS 2007

作者： De Schultz, Max R. O. Mendonça, Alexandre K. I. Carvalho, Felipe G. Furtado, Olinto J. V. Santos, Luiz C. V. Federal University of Santa Catarina Computer Science Department Florianópolis SC Brazil

ISBN: (纸本)9783540736226

Contemporary SoC designs ask for system-level debugging tools suitable to heterogeneous platforms. Such tools will have to rely on some low-level model-driven debugging engine that must be retargetable, since embedded code may run on distinct processors within the same platform. this paper describes a technique for automatically retargeting debugging tools for embedded code inspection. the technique relies on two key ideas: automatic extraction of machine-dependent information from a formal model of the processor and reuse of a conventional binary utility package as implementation infrastructure. the re-targetability of the technique was experimentally validated for targets MIPS, SPARC, PowerPC and i8051. © Springer-Verlag Berlin Heidelberg 2007.

关键词： embedded systems

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An automatically-retargetable time-constraint-driven instruction scheduler for post-compiling optimization of embedded code

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7th international workshop on embedded computer systems: architectures, modeling, and simulation, SAMOS 2007

作者： José, O. Carlomagno F. Santos, Luiz F. P. Dos Santos, Luiz C. V. Federal University of Santa Catarina Computer Science Department Florianópolis SC Brazil

ISBN: (纸本)9783540736226

Although SoC design space exploration requires retargetable tools and real-time constraint awareness, conventional compiler infrastructure barely provides both. this paper proposes a novel, automatically retargetable, time-constraint aware instruction scheduler to fulfill both needs. the tool is based upon a unified representation of instruction precedence and timing constraints. It relies on a formal model of the target processor, written in an architecture description language. Experimental results show that the technique not only handles time-constraint analysis efficiently, but also exploits them successfully to guide code optimization. To give proper evidence of retargetability, we present results for the processors MIPS, PowerPC and SPARC. We obtained speed-ups of 1.18 to 1.23 over pre-optimized code. © Springer-Verlag Berlin Heidelberg 2007.

关键词： embedded systems

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Proposal of Dynamic Module Library for System Level modeling and simulation of Dynamically Reconfigurable systems

Proposal of Dynamic Module Library for System Level Modeling...

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international Conference on VLSI Design

作者： Kenji Asano Junji Kitamichi Kenichi Kuroda NEC Electronics Corporation Limited Kawasaki Kanagawa Japan School of Computer Science and Engineering University of Aizu Fukushima Japan

ISBN: (纸本)9780769527628;0769527620

In this paper, we propose a library for the system level modeling and simulation of dynamically reconfigurable architectures (DRAs). Using the proposed library, the designer can model the system specifications including modules for the dynamic generation and elimination that are needed in the design of dynamically reconfigurable systems. In addition, we evaluate the proposed library by the modeling and simulation of sample circuits, such as multi-context DRA and partially DRA. Using the proposed library, we can model the system specifications as much the same amount as a detailed description, such as one using multiplexers and de-multiplexers, which is a modeling formula for describing multi-context DRA. Under some conditions, higher-speed simulation is possible using the proposed library

关键词： Proposals Circuit simulation System-level design Computational modeling computer simulation Multiplexing Software libraries embedded software Reconfigurable architectures Design methodology

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A linear complexity algorithm for the generation of multiple input single output instructions of variable size

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7th international workshop on embedded computer systems: architectures, modeling, and simulation, SAMOS 2007

作者： Galuzzi, Carlo Bertels, Koen Vassiliadis, Stamatis Computer Engineering EEMCS TU Delft

ISBN: (纸本)9783540736226

the Instruction-Set extension problem has been one of the major topics in the last years and it is the addition of a set of new complex instructions to a given Instruction-Set. this problem in its general formulation requires an exhaustive search of the design space to identify the candidate instructions. this search turns into an exponential complexity of the solution. In this paper we propose an algorithm for the generation of Multiple Input Single Output instructions of variable size which can be directly selected or combined for Instruction-Set extension. Additionally, the algorithm is suitable for inclusion in a design flow for automatic generation of MIMO instructions. the proposed algorithm is not restricted to basic-block level and has linear complexity with the number of processed elements. © Springer-Verlag Berlin Heidelberg 2007.

关键词： Algorithms

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Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics: Preface

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Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2007年 4599 LNCS卷 VII-VIII页

作者： Berekovic, Mladen Hamalainen, Timo D.

No abstract available

ISBN: (纸本)9783540736226

No abstract available

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SC2SCFL: Automated SystemC to SystemC double-struck F signdouble-struck L sign translation

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7th international workshop on embedded computer systems: architectures, modeling, and simulation, SAMOS 2007

作者： Man, Ka Lok Fedeli, Andrea Mercaldi, Michele Boubekeur, Menouer Schellekens, Michel Cork Ireland Italy M.O.S.T Turin Italy

ISBN: (纸本)9783540736226

SystemCdouble-struck F signdouble-struck L sign is the formalisation of a reasonable subset of SystemC based on classical process algebras. During the last few years, SystemC double-struck F signdouble-struck L sign has been successfully used to give formal specifications of SystemC designs. For formal analysis purposes, so far, users have been required to transform manually their SystemC codes into corresponding SystemCdouble-struck F signdouble-struck L sign specifications. To verify some desired properties of SystemC double-struck F signdouble-struck L sign specifications using existing formal verification tools (e.g. NuSMV and SPIN), similarly, manual translations have been needed for turning SystemC double-struck F signdouble-struck L sign specifications into corresponding terms of the input language (e.g. SMV and PROMELA) of the selected formal verification tool. Since manual transformation and translations between SystemC codes, SystemC specifications, and various formalisms are quite laborious and therefore error-prone, these translations have to be made as much automatic as possible. the first step of the research in these directions is to automate the transformation from SystemC codes to SystemC specifications. In this paper, we present SC2SCFL (an automatic translation tool), which converts SystemC codes into corresponding SystemC double-struck F signdouble-struck L sign specifications. © Springer-Verlag Berlin Heidelberg 2007.

关键词： computer systems

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Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level simulation and Test Generation

Fault Coverage and Fault Efficiency of Transistor Shorts usi...

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international Conference on VLSI Design

作者： Yoshinobu Higami Kewal K. Saluja Hiroshi Takahashi Yuzo Takamatsu Graduate School of Science and Engineering Ehime University Japan

ISBN: (纸本)9780769527628;0769527620

this paper proposes a theory of transistor short faults and their detection in logic test environment. the transistor short models were defined, and the characteristics of equivalent faults and redundant faults were revealed. Also presented were a stuck-at fault simulation method and a test generation method that uses only the gate-level description of the circuits while dealing with transistor short faults. Experimental results for ISCAS benchmark circuits were presented to demonstrate the effectiveness of the methodology proposed in this paper

关键词： Circuit faults Logic testing Circuit testing Circuit simulation Computational modeling Benchmark testing Fault diagnosis Large scale integration computer simulation Electrical fault detection

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Algorithm-level Optimization for Real-time H.264/AVC Encoder

Algorithm-level Optimization for Real-time H.264/AVC Encoder

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international Conference on systems, Signals and Image Processing, IWSSIP

作者： Seung-Hwan Kim Yo-Sung Ho Department of Information and Communications Gwangju Institute of Science and Technology Gwangju South Korea

the H.264 standard achieves higher compression efficiency than previous video coding standards with the rate-distortion optimized (RDO) method for mode decision. the outstanding coding performance of H.264, however, comes at the cost of significantly increased complexity. In this paper, we present algorithm-level optimization methods: input parameter selection, fast inter-mode decision, and efficient combination of motion estimation and mode decision. simulation results show that our optimized H.264 encoder achieves realtime encoding for video graphics array (VGA) and extended graphics array (XGA) on a commercial personal computer without introducing serious quality degradations.

关键词： Automatic voltage control Optimization methods computer graphics Video coding Rate-distortion Costs Motion estimation Computational modeling computer simulation Encoding

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