In recent years designers of embeddedcomputersystems face a tremendous growth in complexity of their systems. this, together withthe fact that the used system clock frequencies rise and that the real time required ...
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ISBN:
(纸本)1424401550
In recent years designers of embeddedcomputersystems face a tremendous growth in complexity of their systems. this, together withthe fact that the used system clock frequencies rise and that the real time required to see features start up and work correctly in an embedded system also increases, let skyrocket the simulation times of event based simulation engines. Performing these simulations on register transfer level (RTL), however, is crucial to achieve functional verification of embeddedcomputersystems. the acceleration of such event based simulations thus is the aim of the work presented in this paper. To this end a methodology called clock suppression is presented and thoroughly discussed. To underpin the feasibility and performance of this approach, evaluation results of simulation experiments for several designs will be shown.
this paper describes security features of ZigBee and Bluetooth PAN wireless networks. On examples of those two wireless systems are demonstrated challenges associated with utilization of present wireless systems for a...
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ISBN:
(纸本)3540364102
this paper describes security features of ZigBee and Bluetooth PAN wireless networks. On examples of those two wireless systems are demonstrated challenges associated with utilization of present wireless systems for applications requiring secure data exchange. Recent penetration of wireless technologies into building and process automation applications even increases the need to fully understand the limitations of the security concepts used.
the multimedia capabilities in battery powered mobile communication devices should be provided at high energy efficiency. Consequently, the hardware is usually implemented using low-power technology and the hardware a...
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ISBN:
(纸本)3540364102
the multimedia capabilities in battery powered mobile communication devices should be provided at high energy efficiency. Consequently, the hardware is usually implemented using low-power technology and the hardware architectures are optimized for embedded computing. Software architectures, on the other hand, are not embedded system specific, but closely resemble each other for any computing device. the popular architectural principle, software layering, is responsible for much of the overheads, and explains the stagnation of active usage times of mobile devices. In this paper, we consider the observed developments against the needs of multimedia applications in mobile communication devices and quantify the overheads in reference implementations.
High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such high-level modelin...
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ISBN:
(纸本)1424401550
High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such high-level modeling and simulation methods is that they should yield trustworthy performance estimations. this requires validation (if possible) and calibration of the simulation models, which are two aspects that have not yet been widely addressed in the system-level community. this paper presents an initial attempt to provide support for calibrating various model components of a system-level performance model. We discuss these model calibration mechanisms in the context of our Sesame system-level simulation framework. An illustrative case study will also be presented to indicate the merits of model calibration.
We present SimGate - a full-system simulator for the Stargate intermediate-level, resource-constrained, sensor network device. We empirically evaluate the accuracy and performance of the system in isolation as well as...
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ISBN:
(纸本)1424401550
We present SimGate - a full-system simulator for the Stargate intermediate-level, resource-constrained, sensor network device. We empirically evaluate the accuracy and performance of the system in isolation as well as coupled with simulated Mica2 motes. Our system is functionally correct and achieves accurate cycle estimation (i.e. cycle-close). Moreover, the overhead of simulated execution is modest with respect to previously published work.
We present a soft error rate (SER) analysis methodology within a simulation and design environment that covers a broad spectrum of design problems and parameters. Our approach includes modeling of the particle hit at ...
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ISBN:
(纸本)3540364102
We present a soft error rate (SER) analysis methodology within a simulation and design environment that covers a broad spectrum of design problems and parameters. Our approach includes modeling of the particle hit at the transistor level, fast Monte-Carlo type simulation to obtain the latching probability of a particle hit on all nodes of the circuit, embedded timing analysis to obtain the latching window, and fine-grained accounting of the electrical masking effects to account for boththe effects of scaling and of pulse duration versus the period of the system clock to get an estimate of the maximum SER of the circuit. this approach has been implemented in CARROT and placed under a broad design environment to assess design tradeoffs with SER as a parameter.
High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such high-level modelin...
详细信息
High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such high-level modeling and simulation methods is that they should yield trustworthy performance estimations. this requires validation ( if possible) and calibration of the simulation models, which are two aspects that have not yet been widely addressed in the system-level community. this article presents a number of mechanisms for both calibrating isolated model components as well as a system-level performance model as a whole. We discuss these model calibration mechanisms in the context of our Sesame system-level simulation framework. Two illustrative case studies will also be presented to indicate the merits of model calibration.
Soft real-time systems are often analysed using hard realtime techniques, which are not suitable to take into account the deadline misses rate allowed in such systems. therefore, the resulting system is over-dimension...
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ISBN:
(纸本)3540364102
Soft real-time systems are often analysed using hard realtime techniques, which are not suitable to take into account the deadline misses rate allowed in such systems. therefore, the resulting system is over-dimensioned, thus expensive. To appropriately dimension soft real-time systems, adequate models, capturing their varying runtime behaviour, are needed. By using the concepts of a mathematically defined language, we provide a modelling approach based on patterns that are able to express the variations appearing in the system timing behaviour. Based on these modelling patterns, models can be easily created and are amenable to average case performance evaluation. By the means of a case study, we show the type of results that can be obtained from such an evaluation and how these results are used to dimension the system.
this paper proposes a new integration technique, called IRIS (Integrated Register allocation and Instruction Scheduling), to combine instruction scheduling and register allocation. Both register allocation and instruc...
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ISBN:
(纸本)3540364102
this paper proposes a new integration technique, called IRIS (Integrated Register allocation and Instruction Scheduling), to combine instruction scheduling and register allocation. Both register allocation and instruction scheduling are performed simultaneously at each variable reference where the selection between serialization by scheduling and spilling by register allocation is determined. To make a right selection, the costs of serialization and spilling are estimated with a cost model proposed to reduce the complexity of the estimation. Experiments show that IRIS achieves significant improvements when compared to widely-used existing techniques.
In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. the memory architecture is integrated with SIMD ex...
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ISBN:
(纸本)3540364102
In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. the memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache-architectures and perform exhaustive simulations. the simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. the multilevel cache-based architecture processes approximately 17 frames/s compared to 1922 frames/s for 512 KB dedicated on-chip zero-wait state memory. thus it is difficult to justify using dedicated memory for this kind of embeddedsystems, when energy consumption and cost of implementation are also considered.
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