检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

344 篇 会议
16 册 图书
16 篇 期刊文献

馆藏范围

376 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

287 篇 工学
- 262 篇 计算机科学与技术...
- 153 篇 软件工程
- 70 篇 信息与通信工程
- 39 篇 电子科学与技术（可...
- 37 篇 电气工程
- 27 篇 控制科学与工程
- 9 篇 安全科学与工程
- 5 篇 机械工程
- 5 篇 动力工程及工程热...
- 4 篇 化学工程与技术
- 2 篇 光学工程
- 2 篇 仪器科学与技术
- 2 篇 建筑学
- 2 篇 土木工程
- 2 篇 交通运输工程
- 2 篇 环境科学与工程（可...
- 2 篇 生物医学工程（可授...
- 2 篇 网络空间安全
71 篇 理学
- 54 篇 数学
- 15 篇 系统科学
- 7 篇 统计学（可授理学、...
- 6 篇 物理学
- 4 篇 生物学
- 2 篇 化学
25 篇 管理学
- 23 篇 管理科学与工程(可...
- 11 篇 工商管理
- 3 篇 图书情报与档案管...
4 篇 经济学
- 4 篇 应用经济学
3 篇 法学
- 3 篇 社会学
3 篇 医学
2 篇 教育学
- 2 篇 教育学

主题

44 篇 embedded systems
38 篇 computer archite...
29 篇 computational mo...
11 篇 data communicati...
11 篇 hardware
9 篇 simulation and m...
9 篇 software enginee...
8 篇 computer simulat...
8 篇 simulation
8 篇 system-on-chip
7 篇 computer hardwar...
7 篇 program processo...
7 篇 integrated circu...
7 篇 wireless telecom...
6 篇 analytical model...
6 篇 embedded system
6 篇 field programmab...
5 篇 circuit simulati...
5 篇 information syst...
5 篇 application soft...

机构

3 篇 politecnico di t...
3 篇 univ victoria de...
2 篇 katholieke univ ...
2 篇 beijing institut...
2 篇 univ aachen rhei...
2 篇 university of go...
2 篇 federal universi...
2 篇 seoul natl univ ...
2 篇 vrije univ bruss...
2 篇 univ amsterdam i...
2 篇 beijing institut...
2 篇 tampere univ tec...
2 篇 computer enginee...
2 篇 intel corp mobil...
2 篇 school of comput...
2 篇 department of co...
2 篇 univ wisconsin d...
2 篇 vienna univ tech...
2 篇 tampere univ tec...
2 篇 sandbridge techn...

作者

6 篇 pimentel andy d.
6 篇 hamalainen timo ...
5 篇 catthoor francky
5 篇 vassiliadis stam...
4 篇 thompson mark
4 篇 berekovic mladen
4 篇 polstra simon
4 篇 takala jarmo
4 篇 hannikainen mark...
3 篇 erbas cagkan
3 篇 dutt nikil
3 篇 blume holger
3 篇 kohvakka mikko
3 篇 bertels koen
3 篇 vassiliadis s
2 篇 salminen erno
2 篇 herber paula
2 篇 gurun selim
2 篇 wong stephan
2 篇 jhon chu shik

语言

375 篇 英文
1 篇 中文

检索条件"任意字段=6th International Workshop on Embedded Computer Systems - Architectures, Modeling and Simulation"

共 376 条记录，以下是191-200 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Model Based Test Generation for Microprocessor Architecture Validation

Model Based Test Generation for Microprocessor Architecture ...

引用

international Conference on VLSI Design

作者： Sreekumar V. Kodakara Deepak A. Mathaikutty Ajit Dingankar Sandeep Shukla David Lilja The University of Minnesota Minneapolis MN CESCA Virginia Tech. Blacksburg VA USA Validation Technology Intel Corporation Folsom CA USA CESCA Virginia Tech. Blacksburg VA University of Minnesota Minneapolis MN USA

ISBN: (纸本)9780769527628;0769527620

Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used in simulation based validation, like simulators and test generators, to validate the system, architecture, microcode, and RTL abstractions of the processor, were manually derived from the specification document. the incomplete informal specification document along with manual translation introduces inconsistency and bugs in the validation collaterals, resulting in increased cost and time to validate the processor. We envision a novel metamodeling based microprocessor modeling and validation environment (MMV) to address this problem. MMV provides a language independent modeling environment to describe the processor at various abstraction levels, a refinement flow to consistently move from one abstraction to the next lower abstraction and code generators to automatically generate the validation collaterals from the models. As a first step towards our vision, in this paper, we describe architectural modeling in MMV and automatic generation of random and coverage directed test suites from the models. We demonstrate the practicality of our approach for validating real world instruction set architectures (ISA) by modeling and generating test cases for eight complex instructions from Intel 1 reg virtualization technology

关键词： Testing Microprocessors Trademarks Analytical models computer bugs Time to market Cost function Product development Natural languages Very large scale integration

来源：评论

学校读者我要写书评

暂无评论

Equivalence and Dominance Relations Between Fault Pairs and their Use in Fault Pair Collapsing for Fault Diagnosis

Equivalence and Dominance Relations Between Fault Pairs and ...

引用

international Conference on VLSI Design

作者： Irith Pomeranz Sudhakar M. Reddy School of Electrical & Computer Engineering Purdue University West Lafayette IN USA Electrical & Computer Engineering Department University of Iowa IA USA

ISBN: (纸本)9780769527628;0769527620

Equivalence and dominance relations used earlier in fault diagnosis procedures are defined as relations between faults, similar to the relations used for fault collapsing. Since the basic entity of diagnostic fault simulation and test generation is a fault pair, and not a single fault, we introduce a framework where equivalence and dominance relations are defined for fault pairs. Using equivalence and dominance relations between fault pairs, we describe a fault pair collapsing process, where fault pairs are removed from consideration under diagnostic fault simulation and test generation since they are guaranteed to be distinguished when other fault pairs are distinguished. We demonstrate the full extent of fault pair collapsing by considering circuits with small numbers of inputs. We also describe an efficient fault pair collapsing procedure for larger circuits based on structural analysis

关键词： Fault diagnosis Circuit faults Circuit testing Fault detection Circuit simulation Cities and towns Computational modeling

来源：评论

学校读者我要写书评

暂无评论

Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit simulation

Analytical Drain Current Model of Nanoscale Strained-Si/SiGe...

引用

international Conference on VLSI Design

作者： M. Jagadesh Kumar Vivek Venkataraman Susheel Nawal Department of Electrical Engineering Indian Institute of Technology New Delhi India Department of Electrical and Computer Engineering Cornell University Ithaca NY USA

ISBN: (纸本)9780769527628;0769527620

For nanoscale CMOS applications, strained-silicon devices have been receiving considerable attention owing to their potential for achieving higher performance and compatibility with conventional silicon processing. In this work, an analytical model for the output current characteristics (I-V) of nanoscale bulk strained-Si/SiGe MOSFETs, suitable for analog circuit simulation, is developed. We demonstrate significant current enhancement due to strain, even in short channel devices, attributed to the velocity overshoot effect. the accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations

关键词： Analytical models Silicon germanium Germanium silicon alloys MOSFETs Analog circuits Circuit simulation Semiconductor device modeling Nanoscale devices CMOS process Capacitive sensors

来源：评论

学校读者我要写书评

暂无评论

Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs

Test-Length Selection and TAM Optimization for Wafer-Level, ...

引用

international Conference on VLSI Design

作者： Sudarshan Bahukudumbi Krishnendu Chakrabarty Department of Electrical and Computer Engineering Duke University Durham NC USA

ISBN: (纸本)9780769527628;0769527620

Wafer-level testing (wafer sort) is used in the semiconductor industry to reduce packaging and test cost. However, a large number of wafer probe contacts lead to higher yield loss. therefore, it is desirable that the number of chip pins contacted by tester channels during wafer sort be kept small to reduce the yield loss resulting from improper contacts. Since test time and the number of contacted chip pins are major practical constraints for wafer sort, not all scan-based digital tests can be applied to the die-under-test. We propose an optimization framework that addresses test access mechanism (TAM) optimization and test-length selection for wafer-level testing of core-based digital SoCs. the objective here is to design TAM architecture and determine test-lengths for the embedded cores such that the overall SoC defect screening probability at wafer sort is maximized. Defect probabilities for the embedded cores, obtained using statistical yield modeling, are incorporated in the optimization framework. simulation results are presented for five of the ITC'02 SoC Test benchmarks

关键词： Semiconductor device testing Pins Probability Electronics industry Semiconductor device packaging Wafer scale integration Costs Probes Semiconductor device modeling Benchmark testing

来源：评论

学校读者我要写书评

暂无评论

On the Impact of Address Space Assignment on Performance in systems-on-Chip

On the Impact of Address Space Assignment on Performance in ...

引用

international Conference on VLSI Design

作者： G. Hazari M. P. Desai H. Kasture Department of Electrical Engineering Indian Institute of Technology Bombay India

ISBN: (纸本)9780769527628;0769527620

Today, VLSI systems for computationally demanding applications are being built as systems-on-chip (SoCs) with a distributed memory subsystem which is shared by a large number of processing elements. the memory sub-system is a potential performance bottleneck in the system. In this paper, the authors consider such a distributed memory subsystem and study the impact of address space distribution on system performance. For a given application on such a system, we introduce the notion of address assignment quality. We show that this assignment quality metric is strongly correlated with memory subsystem throughput over large regions of the design space. We show this using open loop performance modeling of the memory subsystem, and justify this using a queueing and a Markov chain analysis. Further, we develop a detailed memory subsystem model for a multi-processor simulation system built on the Augmint framework. Using two (highly parallel) applications (matrix multiplication and bubble sort) the authors show that application throughput and assignment quality are strongly correlated over large regions of the design space. We infer that maximization of the assignment quality metric can be a fundamental goal in designing memory subsystems and in developing applications in such systems-on-chip

关键词： throughput Very large scale integration Predictive models Space technology System performance Queueing analysis Extraterrestrial measurements computer applications Distributed computing Performance analysis

来源：评论

学校读者我要写书评

暂无评论

modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design

Modeling of Leakages in Nano-Scale DG MOSFET to Implement Lo...

引用

international Conference on VLSI Design

作者： Deblina Sarkar Samiran Ganguly Deepanjan Datta A. A. P. Sarab Sudeb Dasgupta Department of Electronics and Instrumentation Engineering Indian School of Mines University Dhanbad India Department of Electronics and Computer Engineering Indian Institute of Technology Roorkee India

ISBN: (纸本)9780769527628;0769527620

Double-gate (DG) MOSFET has emerged as one of the most promising devices for logic and memory circuit design in sub 10nm regime. In this paper, we investigate the gate-to-channel leakage, EDT, BTBT and sub-threshold leakage for DG MOSFET. simulations are performed using 2D Poisson-Schrodinger simulator with tight-binding Green's function approach. then we analyze the effect of parameter variation to optimize low leakage SRAM cell using DG devices. the DG device/circuit co-design successfully demonstrates the benefit of using metal gate intrinsic body DG devices which significantly reduces BTBT and EDT in SRAM architecture

关键词： Nanoscale devices MOSFET circuits Power MOSFET Random access memory Circuit simulation Logic devices Logic design Logic circuits Circuit synthesis Green's function methods

来源：评论

学校读者我要写书评

暂无评论

embedded computer systems: architectures, modeling, and simulation: 5th international workshop, SAMOS 2005. Proceedings

Embedded Computer Systems: Architectures, Modeling, and Simu...

引用

5th international workshop on embedded computer systems: architectures, modeling, and simulation, SAMOS 2005

the proceedings contain 49 papers from the embedded computer systems: architectures, modeling, and simulation: 5th international workshop, SAMOS 2005. the topics discussed include: interprocedural optimization for dynamic hardware configurations;reconfigurable embedded systems: an application-oriented perspective on architectures and design techniques;reconfigurable multiple operation array;RAPANUI: rapid prototyping for media processor architecture exploration;data-driven regular reconfigurable arrays: design space exploration and mapping;automatic FIR filter generation for FPGAs;and two-dimensional fast cosine transfrom for vector-STA architectures.

关键词： embedded systems

来源：评论

学校读者我要写书评

暂无评论

European research in embedded systems

European research in embedded systems

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Tsarchopoulos, Panagiotis Embedded Systems Unit European Commission

ISBN: (纸本)3540364102

Digital information technology has revolutionized the world within less than four decades. It has taken the step from mainframe computers, mainly operated as hosts in computing centres, to desktops and laptops, connected by networks and found nearly on all office desks and tables today. computers have become every day tools deeply integrated into all kinds of activities of our life.

关键词：

来源：评论

学校读者我要写书评

暂无评论

On security of PAN wireless systems

On security of PAN wireless systems

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Hyncica, Ondrej Kacz, Peter Fiedler, Petr Bradac, Zdenek Kucera, Pavel Vrba, Radimir Brno Univ Technol Fac Elect Engn & Commun Brno 61200 Czech Republic

ISBN: (纸本)3540364102

this paper describes security features of ZigBee and Bluetooth PAN wireless networks. On examples of those two wireless systems are demonstrated challenges associated with utilization of present wireless systems for applications requiring secure data exchange. Recent penetration of wireless technologies into building and process automation applications even increases the need to fully understand the limitations of the security concepts used.

关键词： Wireless telecommunication systems

来源：评论

学校读者我要写书评

暂无评论

Static energy saving through multi-bank memory architecture

Static energy saving through multi-bank memory architecture

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Lafond, Sebastien Lilius, Johan Turku Ctr Comp Sci Embedded Syst Lab Lemminkaisenkatu 14A FIN-20520 Turku Finland Abo Akad Univ Dept Informat Technol FIN-20520 Turku Finland

ISBN: (纸本)1424401550

Managing the energy consumption of embedded systems has become a major problem with the increasing demand for portable electronic devices. this paper propose a multi-bank memory architecture as a solution to decrease the static energy cost in memory. We set up the equations ruling the optimization problem for decreasing the memory static energy cost, analyze the impact of different parameters on the energy cost and finally present some case study results.

关键词： Memory architecture

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共38页 << < 16 17 18 19 20 21 22 23 24 25 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：