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检索条件"任意字段=6th International Workshop on Embedded Computer Systems - Architectures, Modeling and Simulation"

共 376 条记录，以下是221-230 订阅

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Design of asynchronous embedded processor with new ternary data encoding scheme

Design of asynchronous embedded processor with new ternary d...

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Lee, Je-Hoon Choi, Eun-Ju Cho, Kyoung-Rok Chungbuk Natl Univ Dept Comp & Commun Engn Cheongju Chungbuk Do South Korea

ISBN: (纸本)3540364102

this paper presents a low-power implementation of the asynchronous 8051 processor, called A8051 and it employs a new data encoding method, RT/NRT encoding, to reduce switching activities. the paper focuses on power analysis of the proposed data encoding based on the experimental design of A8051. the proposed data encoding method is devised to meet the DI assumption using Ternary logic. this method reduces not only the number of wires but also the switching activities. In terms of switching activities, the proposed ternary encoding can reduce 26% comparing to conventional ternary encoding. A8051 using RT/NRT encoding shows 24% higher instruction per energy metric comparing to A8051 using dual-rail encoding.

关键词： Program processors

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On-chip communication in run-time assembled reconfigurable systems

On-chip communication in run-time assembled reconfigurable s...

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Sedcole, Pete Cheung, Peter Y. K. Constantinides, George A. Luk, Wayne Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London England Univ London Imperial Coll Sci Technol & Med Dept Comp London England

ISBN: (纸本)1424401550

embedded systems in Field-Programmable Gate Arrays can be customised and adaptive if assembled from modular components at run time. this paper describes techniques for modelling inter-module channel behaviour based on statistical time division multiplexing. Where modules communicate over shared media, the proposed techniques enable systematic development of on-chip communication infrastructure to support run-time instantiation of components. Our techniques also allow system designers to guarantee that logical communication requirements between the adjunct modules can be satisfied by the infrastructure. An in-depth analysis is presented, and then verified with cycle-accurate simulations for the Sonic-on-chip reconfigurable platform for real-time video applications.

关键词： embedded systems

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A table-based application-specific prefetch engine for object-oriented embedded systems

A table-based application-specific prefetch engine for objec...

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Hessabi, Saahin Modarressi, Mehdi Goudarzi, Maziar Javanhemmat, Hani Sharif Univ Technol Dept Comp Engn Tehran Iran

ISBN: (纸本)1424401550

A table-based application-specific data prefetching mechanism is presented in this paper. this mechanism is proposed to improve the performance of the application specific instruction-set processors (ASIP) we develop customized to an object-oriented application. In this approach, we divide the data accesses of a class method into two conditional and unconditional parts. We supply the prefetch engine with the static information about each part to prefetch all data fields of an object required by a class method when the class method is invoked. Effective management of memory access patterns by dividing them based on the method to which they belong and storing the access information of nested loops using a simple structure are the merits of the proposed mechanism. In addition, by adding a prefetch flag to cache blocks, we eliminate a large number of prefetch related tag comparisons. the results show that the proposed mechanism reduces the cache miss ratio and prefetch related tag comparisons on average by 66% and 21%, respectively.

关键词： embedded systems

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Security in Wireless Sensor Networks:: Considerations and experiments

Security in Wireless Sensor Networks:: Considerations and ex...

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Hamalainen, Panu Kuorilehto, Mauri Alho, Timo Hannikainen, Marko Hamalainen, Timo D. Tampere Univ Technol Inst Digital & Comp Syst FI-33101 Tampere Finland

ISBN: (纸本)3540364102

Wireless Sensor Networks (WSN) are seen as attractive solutions for various monitoring and controlling applications, a large part of which require protection. Due to the special characteristics of WSNs, e.g. low processing and energy resources and ad hoc networking, developing a reliable security solution becomes a challenging task. In this paper we survey various security aspects of WSNs, consisting of threats, attacks, and proposed solutions. We also present experiments with our own WSN technology (TUTWSN), concentrating on a centralized key distribution and authentication service. Our experiments suggest that a centralized scheme can be a feasible solution in certain WSN configurations.

关键词： Wireless telecommunication systems

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A solid-state 2-D wind sensor

A solid-state 2-D wind sensor

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Makinwa, K. A. A. Huijsing, Johan H. Hagedoorn, Arend Tech Univ Delft EI EWI DIMES NL-2628 CD Delft Netherlands

ISBN: (纸本)3540364102

this paper describes the industrial realization of a solid-state wind sensor, that is, one without moving parts. the key component of the sensor is a heated silicon chip that is packaged in such a way that it is non-uniformly cooled by the wind. the resulting flow-induced temperature gradient is measured by on-chip temperature sensors. their output is then digitized and processed by a microprocessor in order to determine both wind speed and direction. For wind speeds between 0. 1 and 25m/s, the errors in the computed wind speed and direction are less than 0.5m/s (or +/- 3%) and +/- 3 degrees respectively.

关键词： thermal flow sensor sensor systems

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Preamble sense multiple access (PSMA) for impulse radio ultra wideband sensor networks

Preamble sense multiple access (PSMA) for impulse radio ultr...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Haapola, Jussi Goratti, Leonardo Suliman, Isameldin Rabbachin, Alberto Univ Oulu CWC FIN-90014 Oulu Finland

ISBN: (纸本)3540364102

In this paper we propose preamble sense multiple access (PSMA), a random access MAC protocol capable of clear channel assessment in impulse radio-ultra wideband environment. Full compatibility with IEEE 802.15.4a contention access period is the key design criteria of PSMA, and the goal is to provide an alternative approach to the 802.15.4a envisioned slotted ALOHA and periodic preamble segment transmission schemes. the evaluation of PSMA consists of a traditional throughput analysis as well as energy consumption and delay analysis that takes into account the special features of impulse radio ultra wideband approach. From the analysis we can claim that PSMA has a very good energy and delay performance in addition to satisfactory throughput when the offered traffic to the channel is from low to moderate.

关键词： Wireless telecommunication systems

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LATONA: An advanced server architecture for Ubiquitous Sensor Network

LATONA: An advanced server architecture for Ubiquitous Senso...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Shin, Chi-Hoon Oh, Soo-Cheol Kim, Dae-Won Kim, Sun-Wook Park, Kyoung Kim, Sung-Woon Univ Sci & Technol Dept Comp & Software Engn Taejon 305333 South Korea Elect & Telecommun Res Inst Server Platform Res Team Taejon 305700 South Korea

ISBN: (纸本)3540364102

the emerging Ubiquitous Sensor Network (USN) makes connection less datagrams and short event packets get popular. A large number of short term event packets of USN can cause serious problems, such as interrupt handling overhead and context switching overhead. Furthermore, heavy load of the packet security methods needs enough processing power. then, the more USN develops, the more network overheads would be loaded into host CPU. To solve the problems, we propose a special server component including TOE (TCP/IP Offloading Engine) and H/W IPSec (IP Layer Security) for USN.

关键词： computer architecture

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Area-aware optimizations for resource constrained branch predictors exploited in embedded processors

Area-aware optimizations for resource constrained branch pre...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Salamat, Babak Baniasadi, Amirali Deris, Kaveh Jokar Univ Calif Irvine Sch Informat & Comp Sci Irvine CA 92717 USA Univ Victoria Dept Elect & Comp Engn Victoria BC Canada

ISBN: (纸本)1424401550

Modern embedded processors (e.g., Intel's XScale) use small and simple branch predictors to improve performance. Such predictors impose little area and power overhead but may offer low accuracy. As a result, branch misprediction rate could be high. Such mispredictions result in longer program runtime and wasted activity. To address this inefficiency, we introduce two optimization techniques: First, we introduce an adaptive and low-complexity branch prediction technique. Our branch predictor removes up to a maximum of 50% of the branch mispredictions of a bimodal predictor. this results in improving performance by up to 16%. Second, we present front-end gating techniques and reduce wasted activity up to a maximum of 32%.

关键词： Constrained optimization

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A flash file system to support fast mounting for NAND flash memory based embedded systems

A flash file system to support fast mounting for NAND flash ...

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Park, Song-Hwa Lee, Tae-Hoon Chung, Ki-Dong Pusan Natl Univ Dept Comp Sci Pusan 609735 South Korea

ISBN: (纸本)3540364102

In embedded systems, NAND flash memory is typically used as a storage medium because of its non-volatility, fast access time and solid-state shock resistance. However, it suffers from out-place-up date, limited erase cycles and page based read/write operations. Flash file systems such as JFFS2 and YAFFS, allocate memory spaces using LFS (Log-structured File System) to solve these problems. Because of this, many pieces of a file are scattered through out flash memory. therefore, these file systems should scan entire flash memory to construct the data structures during the mounting. this means that it takes a long time to mount such file systems on a large chip. In this paper, we design and propose a new flash memory file system which targets mobile devices that require fast mounting. We experimented on the file system performance and the results show that we improve the mounting time by 64%-76% as flash usage compared to YAFFS.

关键词： Flash memory

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Hybrid functional and instruction level power modeling for embedded processors

Hybrid functional and instruction level power modeling for e...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Blume, Holger Becker, Daniel Botteck, Martin Brakensiek, Joerg Noll, Tobias G. Univ Aachen Rhein Westfal TH Aachen Chair Elect Engn & Comp Syst D-52062 Aachen Germany Nokia Res Ctr D-44807 Bochum Germany

ISBN: (纸本)3540364102

In this contribution the concept of Functional-Level Power Analysis (FLPA) for power estimation of programmable processors is extended in order to model even embedded general purpose processors. the basic FLPA approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory etc. the power consumption of these blocks is described by parameterized arithmetic models. By application of a parser based automated analysis of assembler codes the input parameters of the arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. For modeling an embedded general purpose processor (here, an ARM940T) the basic FLPA modeling concept had to be extended to a so-called hybrid functional level and instruction level model in order to achieve a good modeling accuracy. the approach is exemplarily demonstrated and evaluated applying a variety of basic digital signal processing tasks ranging from basic filters to complete audio decoders. Estimated power figures for the inspected tasks are compared to physically measured values. A resulting maximum estimation error of less than 8 % is achieved.

关键词： Program processors

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