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检索条件"任意字段=6th International Workshop on Embedded Computer Systems - Architectures, Modeling and Simulation"

共 376 条记录，以下是231-240 订阅

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Mining dynamic document spaces with massively parallel embedded processors

Mining dynamic document spaces with massively parallel embed...

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Jacobs, Jan W. M. Dai, Rui Smit, Gerard J. M. Oce Technol BV NL-5900 MA Venlo Netherlands Natl Univ Singapore Design Technol Inst Fac Engn Singapore 119260 Singapore Univ Twente NL-7500 AE Enschede Netherlands

ISBN: (纸本)3540364102

Currently Oce investigates future document management services. One of these services is accessing dynamic document spaces, i.e. improving the access to document spaces which are frequently updated (like newsgroups). this process is rather computational intensive. this paper describes the research conducted on software development for massively parallel processors. A prototype has been built which processes streams of information from specified newsgroups and transforms them into personal information maps. Although this technology does speed up the training part compared to a general purpose processor implementation its real benefits emerges with larger problem dimensions because of the scalable approach.

关键词： Program processors

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An optimization methodology for memory allocation and task scheduling in SoCs via linear programming

An optimization methodology for memory allocation and task s...

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Ristau, Bastian Fettweis, Gerhard Tech Univ Dresden Vodafone Chair Mobile Commun Syst D-01062 Dresden Germany

ISBN: (纸本)3540364102

Applications for system on chips become more and more complex. Also the number of available components (DSPs, ASICs, Memories, etc.) rises continuously. these facts necessitate a structured method for selecting components, mapping applications and evaluating the chosen configuration and mapping. In this work we present a methodology for the last named. We will consider optimization of memory allocation and task scheduling as a packing problem and minimize needed memory area. the results can be used as one element of an automated performance analysis for a given system on a high abstraction level. this analysis is essential for establishing a framework that iterates over a large quantity of possible systems. Considering a part of the H.264 codec as an example we will illustrate the results. Furthermore we will show that results can be retrieved fast compared to other NP-hard problems due to intelligent formulation of conditions within the linear program.

关键词： Storage allocation (computer)

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Rescheduling for optimized SHA-1 calculation

Rescheduling for optimized SHA-1 calculation

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Chaves, Ricardo Kuzmanov, Georgi Sousa, Leonel Vassiliadis, Stamatis Inst Super Tecn INESC ID P-1000029 Lisbon Portugal Delft Univ Technol Comp Engn Lab NL-2600 GA Delft Netherlands

ISBN: (纸本)3540364102

this paper proposes the rescheduling of the SHA-1 hash function operations on hardware implementations. the proposal is mapped on the Xilinx Virtex II Pro technology. the proposed rescheduling allows for a manipulation of the critical path in the SHA-1 function computation, facilitating the implementation of a more parallelized structure without an increase on the required hardware resources. Two cores have been developed, one that uses a constant initialization vector and a second one that allows for different Initialization Vectors (IV), in order to be used in HMAC and in the processing of fragmented messages. A hybrid software/hardware implementation is also proposed. Experimental results indicate a throughput of 1.4 Gbits/s requiring only 533 slices for a constant IV and 596 for an imputable IV. Comparisons to SHA-1 related art suggest improvements of the throughput /slice metric of 29% against the most recent commercial cores and 59% to the current academia proposals.

关键词： computer hardware

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Reducing execution unit leakage power in embedded processors

Reducing execution unit leakage power in embedded processors

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Homayoun, Houman Baniasadi, Amirali Univ Victoria Dept Elect & Comp Engn Victoria BC Canada

ISBN: (纸本)3540364102

We introduce low-overhead power optimization techniques to reduce leakage power in embedded processors. Our techniques improve previous work by a) taking into account idle time distribution for different execution units, and b) using instruction decode and control dependencies to wakeup the gated (but needed) units as soon as possible. We take into account idle time distribution per execution unit to detect an idle time period as soon as possible. this in turn results in increasing our leakage power savings. In addition, we use information already available in the processor to predict when a gated execution unit will be needed again. this results in early and less costly reactivation of gated execution units. We evaluate our techniques for a representative subset of MiBench benchmarks and for a processor using a configuration similar to Intels Xscale processor. We show that our techniques reduce leakage power considerably while maintaining performance.

关键词： Program processors

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Design, implementation, and experiments on outdoor deployment of wireless sensor network for environmental monitoring

Design, implementation, and experiments on outdoor deploymen...

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Suhonen, Jukka Kohvakka, Mikko Hannikainen, Marko Hamalainen, Timo D. Tampere Univ Technol Inst Comp & Digital Syst FIN-33101 Tampere Finland

ISBN: (纸本)3540364102

this paper presents the design, implementation, and practical real world experiments of an energy optimized multi-hop wireless sensor network (WSN) targeted at environmental monitoring. the WSN is fully autonomous and consists of energy-efficient and scalable communication protocols and low-power hardware platform. Software tools are developed for configuring and analyzing large scale networks. the network has been deployed in outdoor environment consisting of 20 nodes covering over 2 km 2 area. the results show that the multihop network works autonomously, reacts to environmental changes, and is able to operate temperatures down to -30 degrees C. the hardware nodes operating on 433 MHz frequency provide over I km communication distances, while still having sufficient throughput and low energy consumption. the deployed nodes had a lifetime of 6 months with a 1600 mAh battery, while generating 4 packets per minute.

关键词： Wireless telecommunication systems

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Pareto-based application specification for MP-SoC customized run-time management

Pareto-based application specification for MP-SoC customized...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Ykman-Couvreur, Ch. Nollet, V. Marescaux, th. Brockmeyer, E. Catthoor, Fr. Corporaal, H. IMEC VZW Kapeldreef 75 B-3001 Louvain Belgium Katholieke Univ Leuven Leuven Belgium Tech Univ Eindhoven Eindhoven Netherlands

ISBN: (纸本)1424401550

In an MP-SoC environment, a customized run-time management should be incorporated on top of the basic OS services to globally optimize costs (e.g. energy consumption) across all active applications, according to constraints (e.g. performance, user requirements) and available platform resources. To that end, we have proposed a Pareto-based approach combining a design-time application mapping and platform exploration with a low-complexity run-time manager. this allows to alleviate the OS in its run-time decisison making and to avoid conservative worst-case assumptions. In this paper, we focus on the characterization of the Pareto-based application specification, resulting from our design-time exploration. this specification is essential as input for our run-time manager. A representative video codec multimedia application, simulated on our NIP-SoC platform simulator, is used as case study. For the resulting Pareto-based specification, both binary size and performance overhead is negligible.

关键词： System-on-chip

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Real-time embedded system for rear-view mirror overtaking car monitoring

Real-time embedded system for rear-view mirror overtaking ca...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Diaz, Javier Ros, Eduardo Mota, Sonia Agis, Rodrigo Univ Granada Dept Arquitectura & Tecnol Computadores Granada Spain Univ Cordoba Dept Informat & Anal Numer Cordoba Spain

ISBN: (纸本)3540364102

the main goal of an overtaking monitor system is the segmentation and tracking of the overtaking vehicle. this application can be addressed through an optic flow driven scheme. We can focus on the rear. mirror visual field by placing a camera on the top of it. If we drive a car, the ego-motion optic flow pattern is more or less unidirectional, i.e. all the static objects and landmarks move backwards while the overtaking cars move forward towards our vehicle. this well structured motion scenario facilitates the segmentation of regular motion patterns that correspond to the overtaking vehicle. Our approach is based on two main processing stages: first, the computation of optical flow using a novel superpipelined and fully parallelized architecture capable to extract the motion information with a frame-rate up to 148 frames per second at VGA resolution (640x480 pixels). Second, a tracking stage based on motion pattern analysis provides an estimated position of the overtaking car. We analyze the system performance, resources and show some promising results using a bank of overtaking car sequences.

关键词： embedded systems

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Software pipelining support for transport triggered architecture processors

Software pipelining support for transport triggered architec...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Salmela, Perttu Jaaskelainen, Pekka Jarvinen, Tuomas Takala, Jarmo Tampere Univ Technol FIN-33101 Tampere Finland Nokia Technol Platforms FIN-33721 Tampere Finland

ISBN: (纸本)3540364102

Many telecommunication applications, especially baseband processing, and digital signal processing (DSP) applications call for high-performance implementations due to the complexity of algorithms and high throughput requirements. In general, the required performance is obtained with the aid of parallel computational resources. In these application domains, software implementations are often preferred over fixed-function ASICs due to the flexibility and ease of development. Application-specific instruction-set processor (ASIP) architectures can be used to exploit efficiently the inherent parallelism of the algorithms but still maintaining the flexibility. Use of high-level languages to program processor architectures with parallel resources can lead to inefficient resource utilization and, on the other hand, parallel assembly programming is error prone and tedious. In this paper, the inherent problems of parallel programming and software pipelining are mitigated with parallel language syntax and automatic generation of software pipelined code for the iteration kernels. With the aid of the developed tool support, the underlying performance of a processor architecture with parallel resources can be exploited and full utilization of the main processing resources is obtained for pipelined loop kernels. the given examples show that efficiency can be obtained without reducing the performance.

关键词： computer software

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throughput optimization via cache partitioning for embedded multiprocessors

Throughput optimization via cache partitioning for embedded ...

引用

6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Molnos, Anca A. Cotofana, Soirin D. Heijligers, Marc J. M. van Eijndhoven, Jos T. J. Delft Univ Technol Mekelweg 4 NL-2426 CD Delft Netherlands Philips Res Labs NL-5656 AE Eindhoven Netherlands

ISBN: (纸本)1424401550

In embedded multiprocessors cache partitioning is a known technique to eliminate inter-task cache conflicts, so to increase predictability. On such systems, the partitioning ratio is a parameter that should be tuned to optimize performance. In this paper we propose a Simulated Annealing (SA) based heuristic to determine the cache partitioning ratio that maximizes an application's throughput. In its core, the SA method iterates many times over many partitioning ratios, checking the resulted throughput. Hence the throughput of the system has to be estimated very fast, so we utilize a light simulation strategy. the light simulation derives the throughput from tasks I timings gathered off-line. this is possible because in an environment where tasks don't interfere with each other, their performance figures can be used in any possible combination. An application of industrial relevance (H.264 decoder) running on a parallel homogeneous platform is used to demonstrate the proposed method. For the H.264 application 9% throughput improvement is achieved when compared to the throughput obtained using methods of partitioning for the least number of misses. this is a significant improvement as it represents 45% from the theoretical throughput improvement achievable when assuming an infinite cache.

关键词： throughput

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Performance improvements in microprocessor systems utilizing a coprocessor data-path

Performance improvements in microprocessor systems utilizing...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Galanis, Michalis D. Dimitroulakos, Gregory Goutis, Costas E. Univ Patras VLSI Design Lab E&CE Dept Rion 26500 Greece

ISBN: (纸本)1424401550

the speedups achieved in a generic microprocessor system by employing a high-performance data-path are presented in this work. the data-path acts as a coprocessor that accelerates computational intensive kernel regions thereby increasing the overall performance. It is composed by Flexible Computational Components (FCCs) that can realize any two-level template of primitive operations. the automated coprocessor synthesis method and its integration to a design flow for executing applications on the system is presented. Analytical exploration in respect to the type of the custom data-path and to the microprocessor architecture is performed. the overall application speedups of eight real-life applications, relative to the software execution on the microprocessor, are estimated using the design flow. these speedups range from 1.75 to 3.95, having an average value of 2.72, while the overhead in circuit area is small. A comparison with another high-performance data-path showed that the proposed coprocessor achieves better performance while having smaller area-time products for the generated data-paths.

关键词： Coprocessor

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