Soft real-time systems are often analysed using hard realtime techniques, which are not suitable to take into account the deadline misses rate allowed in such systems. therefore, the resulting system is over-dimension...
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ISBN:
(纸本)3540364102
Soft real-time systems are often analysed using hard realtime techniques, which are not suitable to take into account the deadline misses rate allowed in such systems. therefore, the resulting system is over-dimensioned, thus expensive. To appropriately dimension soft real-time systems, adequate models, capturing their varying runtime behaviour, are needed. By using the concepts of a mathematically defined language, we provide a modelling approach based on patterns that are able to express the variations appearing in the system timing behaviour. Based on these modelling patterns, models can be easily created and are amenable to average case performance evaluation. By the means of a case study, we show the type of results that can be obtained from such an evaluation and how these results are used to dimension the system.
In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. the memory architecture is integrated with SIMD ex...
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ISBN:
(纸本)3540364102
In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. the memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache-architectures and perform exhaustive simulations. the simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. the multilevel cache-based architecture processes approximately 17 frames/s compared to 1922 frames/s for 512 KB dedicated on-chip zero-wait state memory. thus it is difficult to justify using dedicated memory for this kind of embeddedsystems, when energy consumption and cost of implementation are also considered.
In this paper, a new methodology is presented for topology optimization of networked embeddedsystems as they occur in automotive and avionic systems and partially in wireless sensor networks. By introducing a model w...
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ISBN:
(纸本)1424401550
In this paper, a new methodology is presented for topology optimization of networked embeddedsystems as they occur in automotive and avionic systems and partially in wireless sensor networks. By introducing a model which is (1.) suitable for heterogeneous networks with different communication bandwidths, (2.) modeling of routing restrictions, and (3.) flexible binding of tasks onto processors, current design issues of networked embeddedsystems can be investigated. On the basis of this model, the presented methodology firstly allocates the required resources which can be communication links as well as computational nodes and secondly binds the functionality onto the nodes and the data dependencies onto the links such that no routing restrictions will be violated or capacities on communication links will be exceeded. By applying Evolutionary Algorithms, we are able to consider multiple objectives simultaneously during the optimization process and allow for a subsequent unbiased decision making. An experimental evaluation as well as a demonstration of a case study from the field of automotive electronics will show the applicability of the presented approach.
Java, with its advantages as being an overspread multiplatform object oriented language, has been gaining popularity in the embedded system market over the years. Furthermore, because of its extra layer of interpretat...
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ISBN:
(纸本)3540364102
Java, with its advantages as being an overspread multiplatform object oriented language, has been gaining popularity in the embedded system market over the years. Furthermore, because of its extra layer of interpretation, it is also believed that it is a slow language while being executed. However, when this execution is done directly in hardware, advantages because of its stack nature start to appear. One of these advantages concerns the memory utilization, impacting in less accesses and cache misses. In this work we analyze this impact in performance and energy consumption, comparing a Java processor with a RISC one based on a MIPS with similar characteristics.
the Model Driven Development (MDD) paradigm stimulates the use of models as the main artifacts for software development. these models can be situated at high levels of abstraction, close to the application's busin...
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ISBN:
(纸本)3540364102
the Model Driven Development (MDD) paradigm stimulates the use of models as the main artifacts for software development. these models can be situated at high levels of abstraction, close to the application's business domain. Many consecutive automatic transformations (a transformation chain) can be applied to these models to add the necessary details in order to generate a concrete implementation. this means that a large part of the total development effort is relocated to the development of transformations and hence we should have the necessary tooling support for designing transformation chains. In this paper we propose a metamodel for a transformation chain modeling language that enables implementation independent composition of transformations. We also propose a concrete syntax for this language that is based on UML activity diagrams.
this paper describes a Sandbridge Sandblaster system implementation including both hardware and software elements for a WiMAX 802.16e system. the system is implemented on the fully functional multithreaded Sandblaster...
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ISBN:
(纸本)3540364102
this paper describes a Sandbridge Sandblaster system implementation including both hardware and software elements for a WiMAX 802.16e system. the system is implemented on the fully functional multithreaded Sandblaster multiprocessor SB3010 SoC chip. the entire communication protocol, physical layer and MAC, has been implemented in software using pure ANSI C programming language and it executes in real time. In this paper, we also present a radio propagation analysis specific to the Samos island at the workshop location, and the DSP execution performance.
In this work we present UML for Hardware Design (UML-HD), a UML profile suitable for Asynchronous Hardware Design and an approach for automatically generating a Hardware Description Language (HDL) model from UML-HD mo...
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ISBN:
(纸本)3540364102
In this work we present UML for Hardware Design (UML-HD), a UML profile suitable for Asynchronous Hardware Design and an approach for automatically generating a Hardware Description Language (HDL) model from UML-HD models. A UML-HD model comprises solely class diagrams and an action language. We use stereotypes in two categories structure and activity - to categorise classes. Structure type stereotypes signify state and activity type signify transitions. the approach is largely inspired by Petri nets. Several model transformations are suggested in this paper, but only code generation to Haste was implemented.
this paper presents automated distribution of embedded real-time applications modeled in Unified modeling Language version 2.0 (UML 2.0). the automated distribution requires methods and tools for design automation, as...
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ISBN:
(纸本)3540364102
this paper presents automated distribution of embedded real-time applications modeled in Unified modeling Language version 2.0 (UML 2.0). the automated distribution requires methods and tools for design automation, as well as the run-time environment for the distributed execution on the target platform. Executable application code is generated from UML models, and UML with a custom profile is used to abstract hardware architecture and configure application mapping. For experimenting, a full featured WLAN terminal was designed in UML and implemented as a distributed multiprocessor system-on-chip (SoC) on an FPGA prototype platform. Measurements show that a 50-70% reduction in protocol delays is achived with distribution, and delay variations are reduced 45-85%.
Model-Driven Development (MDD) is a software development paradigm that promotes the use of models at different levels of abstraction and perform transformations between them to derive one or more concrete application ...
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ISBN:
(纸本)3540364102
Model-Driven Development (MDD) is a software development paradigm that promotes the use of models at different levels of abstraction and perform transformations between them to derive one or more concrete application implementations. In this paper we analyze the current status of MDD regarding its applicability for the development of Real-Time embedded Software. We discuss different modeling framework approaches used to specify the various models, and compare OMG/MDA-based approaches (MOF, UML Profiles and executable UML) with a generic MDD-based approach (GME). Finally, we identify the key challenges for future MDD research in order to successfully apply MDD within RTES Development. these challenges are mainly situated in the field of modeling and standardization of abstraction levels, model transformations and code generation, traceability, and integration of existing software within the MDD development process
Energetic-particle induced soft errors in on-chip cache memories have become a major challenge in designing new generation reliable microprocessors. Uniformly applying conventional protection schemes such as error cor...
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ISBN:
(纸本)1424401550
Energetic-particle induced soft errors in on-chip cache memories have become a major challenge in designing new generation reliable microprocessors. Uniformly applying conventional protection schemes such as error correcting codes (ECC) to SRAM caches may not be practical where performance, power, and die area are highly constrained, especially for embeddedsystems. In this paper, we propose to analyze the lifetime behavior of the data cache to identify its temporal vulnerability. For this vulnerability analysis, we develop a new lifetime model. Based on the new lifetime model, we evaluate the effectiveness of several existing schemes in reducing the vulnerability of the data cache. Furthermore, we propose to periodically invalidate clean cache lines to reduce the probability of errors being read in by the CPU. Combined with previously proposed early writeback strategies [1], our schemes achieve a substantially low vulnerability in the data cache, which indicate the necessity of different protection schemes for data items during various phases in their lifetime.
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