the recent spectacular progress in modern microelectronics created a big stimulus towards development of mobile, autonomous, embedded and re-configurable systems, but also resulted in man), difficult to solve issues, ...
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ISBN:
(纸本)1424401550
the recent spectacular progress in modern microelectronics created a big stimulus towards development of mobile, autonomous, embedded and re-configurable systems, but also resulted in man), difficult to solve issues, as power and energy crisis or increased leakage power, that are especially serious for this sort of systems. What prevents the (re)configurable heterogeneous embeddedsystems from becoming one of the main practically used paradigms is mainly inadequate support of the development methodologies and EDA-tools for efficient mapping of applications and producing power, energy, and speed optimized systems. As a part of our research that aims at development of effective methods and EDA-tools for the heterogeneous (re-)configurable embedded system synthesis, we performed a comparative analysis of several representative commercial and academic synthesis methods and tools for the FPGA-targeted controller synthesis. In this paper, the automatic hardware synthesis for the heterogeneous embeddedsystems is considered, when focusing on the efficient multi-objective controller synthesis. In particular, a part of results and conclusions from our analysis, and effective solutions of some problems observed are discussed.
this paper presents a low-power implementation of the asynchronous 8051 processor, called A8051 and it employs a new data encoding method, RT/NRT encoding, to reduce switching activities. the paper focuses on power an...
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ISBN:
(纸本)3540364102
this paper presents a low-power implementation of the asynchronous 8051 processor, called A8051 and it employs a new data encoding method, RT/NRT encoding, to reduce switching activities. the paper focuses on power analysis of the proposed data encoding based on the experimental design of A8051. the proposed data encoding method is devised to meet the DI assumption using Ternary logic. this method reduces not only the number of wires but also the switching activities. In terms of switching activities, the proposed ternary encoding can reduce 26% comparing to conventional ternary encoding. A8051 using RT/NRT encoding shows 24% higher instruction per energy metric comparing to A8051 using dual-rail encoding.
embeddedsystems in Field-Programmable Gate Arrays can be customised and adaptive if assembled from modular components at run time. this paper describes techniques for modelling inter-module channel behaviour based on...
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ISBN:
(纸本)1424401550
embeddedsystems in Field-Programmable Gate Arrays can be customised and adaptive if assembled from modular components at run time. this paper describes techniques for modelling inter-module channel behaviour based on statistical time division multiplexing. Where modules communicate over shared media, the proposed techniques enable systematic development of on-chip communication infrastructure to support run-time instantiation of components. Our techniques also allow system designers to guarantee that logical communication requirements between the adjunct modules can be satisfied by the infrastructure. An in-depth analysis is presented, and then verified with cycle-accurate simulations for the Sonic-on-chip reconfigurable platform for real-time video applications.
A table-based application-specific data prefetching mechanism is presented in this paper. this mechanism is proposed to improve the performance of the application specific instruction-set processors (ASIP) we develop ...
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ISBN:
(纸本)1424401550
A table-based application-specific data prefetching mechanism is presented in this paper. this mechanism is proposed to improve the performance of the application specific instruction-set processors (ASIP) we develop customized to an object-oriented application. In this approach, we divide the data accesses of a class method into two conditional and unconditional parts. We supply the prefetch engine withthe static information about each part to prefetch all data fields of an object required by a class method when the class method is invoked. Effective management of memory access patterns by dividing them based on the method to which they belong and storing the access information of nested loops using a simple structure are the merits of the proposed mechanism. In addition, by adding a prefetch flag to cache blocks, we eliminate a large number of prefetch related tag comparisons. the results show that the proposed mechanism reduces the cache miss ratio and prefetch related tag comparisons on average by 66% and 21%, respectively.
Wireless Sensor Networks (WSN) are seen as attractive solutions for various monitoring and controlling applications, a large part of which require protection. Due to the special characteristics of WSNs, e.g. low proce...
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ISBN:
(纸本)3540364102
Wireless Sensor Networks (WSN) are seen as attractive solutions for various monitoring and controlling applications, a large part of which require protection. Due to the special characteristics of WSNs, e.g. low processing and energy resources and ad hoc networking, developing a reliable security solution becomes a challenging task. In this paper we survey various security aspects of WSNs, consisting of threats, attacks, and proposed solutions. We also present experiments with our own WSN technology (TUTWSN), concentrating on a centralized key distribution and authentication service. Our experiments suggest that a centralized scheme can be a feasible solution in certain WSN configurations.
this paper describes the industrial realization of a solid-state wind sensor, that is, one without moving parts. the key component of the sensor is a heated silicon chip that is packaged in such a way that it is non-u...
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ISBN:
(纸本)3540364102
this paper describes the industrial realization of a solid-state wind sensor, that is, one without moving parts. the key component of the sensor is a heated silicon chip that is packaged in such a way that it is non-uniformly cooled by the wind. the resulting flow-induced temperature gradient is measured by on-chip temperature sensors. their output is then digitized and processed by a microprocessor in order to determine both wind speed and direction. For wind speeds between 0. 1 and 25m/s, the errors in the computed wind speed and direction are less than 0.5m/s (or +/- 3%) and +/- 3 degrees respectively.
In this paper we propose preamble sense multiple access (PSMA), a random access MAC protocol capable of clear channel assessment in impulse radio-ultra wideband environment. Full compatibility with IEEE 802.15.4a cont...
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ISBN:
(纸本)3540364102
In this paper we propose preamble sense multiple access (PSMA), a random access MAC protocol capable of clear channel assessment in impulse radio-ultra wideband environment. Full compatibility with IEEE 802.15.4a contention access period is the key design criteria of PSMA, and the goal is to provide an alternative approach to the 802.15.4a envisioned slotted ALOHA and periodic preamble segment transmission schemes. the evaluation of PSMA consists of a traditional throughput analysis as well as energy consumption and delay analysis that takes into account the special features of impulse radio ultra wideband approach. From the analysis we can claim that PSMA has a very good energy and delay performance in addition to satisfactory throughput when the offered traffic to the channel is from low to moderate.
the emerging Ubiquitous Sensor Network (USN) makes connection less datagrams and short event packets get popular. A large number of short term event packets of USN can cause serious problems, such as interrupt handlin...
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ISBN:
(纸本)3540364102
the emerging Ubiquitous Sensor Network (USN) makes connection less datagrams and short event packets get popular. A large number of short term event packets of USN can cause serious problems, such as interrupt handling overhead and context switching overhead. Furthermore, heavy load of the packet security methods needs enough processing power. then, the more USN develops, the more network overheads would be loaded into host CPU. To solve the problems, we propose a special server component including TOE (TCP/IP Offloading Engine) and H/W IPSec (IP Layer Security) for USN.
Modern embedded processors (e.g., Intel's XScale) use small and simple branch predictors to improve performance. Such predictors impose little area and power overhead but may offer low accuracy. As a result, branc...
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ISBN:
(纸本)1424401550
Modern embedded processors (e.g., Intel's XScale) use small and simple branch predictors to improve performance. Such predictors impose little area and power overhead but may offer low accuracy. As a result, branch misprediction rate could be high. Such mispredictions result in longer program runtime and wasted activity. To address this inefficiency, we introduce two optimization techniques: First, we introduce an adaptive and low-complexity branch prediction technique. Our branch predictor removes up to a maximum of 50% of the branch mispredictions of a bimodal predictor. this results in improving performance by up to 16%. Second, we present front-end gating techniques and reduce wasted activity up to a maximum of 32%.
In embeddedsystems, NAND flash memory is typically used as a storage medium because of its non-volatility, fast access time and solid-state shock resistance. However, it suffers from out-place-up date, limited erase ...
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ISBN:
(纸本)3540364102
In embeddedsystems, NAND flash memory is typically used as a storage medium because of its non-volatility, fast access time and solid-state shock resistance. However, it suffers from out-place-up date, limited erase cycles and page based read/write operations. Flash file systems such as JFFS2 and YAFFS, allocate memory spaces using LFS (Log-structured File System) to solve these problems. Because of this, many pieces of a file are scattered through out flash memory. therefore, these file systems should scan entire flash memory to construct the data structures during the mounting. this means that it takes a long time to mount such file systems on a large chip. In this paper, we design and propose a new flash memory file system which targets mobile devices that require fast mounting. We experimented on the file system performance and the results show that we improve the mounting time by 64%-76% as flash usage compared to YAFFS.
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