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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Shin, Chi-Hoon Oh, Soo-Cheol Kim, Dae-Won Kim, Sun-Wook Park, Kyoung Kim, Sung-Woon Univ Sci & Technol Dept Comp & Software Engn Taejon 305333 South Korea Elect & Telecommun Res Inst Server Platform Res Team Taejon 305700 South Korea

ISBN: (纸本)3540364102

the emerging Ubiquitous Sensor Network (USN) makes connection less datagrams and short event packets get popular. A large number of short term event packets of USN can cause serious problems, such as interrupt handling overhead and context switching overhead. Furthermore, heavy load of the packet security methods needs enough processing power. then, the more USN develops, the more network overheads would be loaded into host CPU. To solve the problems, we propose a special server component including TOE (TCP/IP Offloading Engine) and H/W IPSec (IP Layer Security) for USN.

关键词： computer architecture

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A flash file system to support fast mounting for NAND flash memory based embedded systems

A flash file system to support fast mounting for NAND flash ...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Park, Song-Hwa Lee, Tae-Hoon Chung, Ki-Dong Pusan Natl Univ Dept Comp Sci Pusan 609735 South Korea

ISBN: (纸本)3540364102

In embedded systems, NAND flash memory is typically used as a storage medium because of its non-volatility, fast access time and solid-state shock resistance. However, it suffers from out-place-up date, limited erase cycles and page based read/write operations. Flash file systems such as JFFS2 and YAFFS, allocate memory spaces using LFS (Log-structured File System) to solve these problems. Because of this, many pieces of a file are scattered through out flash memory. therefore, these file systems should scan entire flash memory to construct the data structures during the mounting. this means that it takes a long time to mount such file systems on a large chip. In this paper, we design and propose a new flash memory file system which targets mobile devices that require fast mounting. We experimented on the file system performance and the results show that we improve the mounting time by 64%-76% as flash usage compared to YAFFS.

关键词： Flash memory

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Reducing execution unit leakage power in embedded processors

Reducing execution unit leakage power in embedded processors

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Homayoun, Houman Baniasadi, Amirali Univ Victoria Dept Elect & Comp Engn Victoria BC Canada

ISBN: (纸本)3540364102

We introduce low-overhead power optimization techniques to reduce leakage power in embedded processors. Our techniques improve previous work by a) taking into account idle time distribution for different execution units, and b) using instruction decode and control dependencies to wakeup the gated (but needed) units as soon as possible. We take into account idle time distribution per execution unit to detect an idle time period as soon as possible. this in turn results in increasing our leakage power savings. In addition, we use information already available in the processor to predict when a gated execution unit will be needed again. this results in early and less costly reactivation of gated execution units. We evaluate our techniques for a representative subset of MiBench benchmarks and for a processor using a configuration similar to Intels Xscale processor. We show that our techniques reduce leakage power considerably while maintaining performance.

关键词： Program processors

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Design, implementation, and experiments on outdoor deployment of wireless sensor network for environmental monitoring

Design, implementation, and experiments on outdoor deploymen...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Suhonen, Jukka Kohvakka, Mikko Hannikainen, Marko Hamalainen, Timo D. Tampere Univ Technol Inst Comp & Digital Syst FIN-33101 Tampere Finland

ISBN: (纸本)3540364102

this paper presents the design, implementation, and practical real world experiments of an energy optimized multi-hop wireless sensor network (WSN) targeted at environmental monitoring. the WSN is fully autonomous and consists of energy-efficient and scalable communication protocols and low-power hardware platform. Software tools are developed for configuring and analyzing large scale networks. the network has been deployed in outdoor environment consisting of 20 nodes covering over 2 km 2 area. the results show that the multihop network works autonomously, reacts to environmental changes, and is able to operate temperatures down to -30 degrees C. the hardware nodes operating on 433 MHz frequency provide over I km communication distances, while still having sufficient throughput and low energy consumption. the deployed nodes had a lifetime of 6 months with a 1600 mAh battery, while generating 4 packets per minute.

关键词： Wireless telecommunication systems

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Hybrid functional and instruction level power modeling for embedded processors

Hybrid functional and instruction level power modeling for e...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Blume, Holger Becker, Daniel Botteck, Martin Brakensiek, Joerg Noll, Tobias G. Univ Aachen Rhein Westfal TH Aachen Chair Elect Engn & Comp Syst D-52062 Aachen Germany Nokia Res Ctr D-44807 Bochum Germany

ISBN: (纸本)3540364102

In this contribution the concept of Functional-Level Power Analysis (FLPA) for power estimation of programmable processors is extended in order to model even embedded general purpose processors. the basic FLPA approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory etc. the power consumption of these blocks is described by parameterized arithmetic models. By application of a parser based automated analysis of assembler codes the input parameters of the arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. For modeling an embedded general purpose processor (here, an ARM940T) the basic FLPA modeling concept had to be extended to a so-called hybrid functional level and instruction level model in order to achieve a good modeling accuracy. the approach is exemplarily demonstrated and evaluated applying a variety of basic digital signal processing tasks ranging from basic filters to complete audio decoders. Estimated power figures for the inspected tasks are compared to physically measured values. A resulting maximum estimation error of less than 8 % is achieved.

关键词： Program processors

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Accurate and scalable simulation of network of heterogeneous sensor devices

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JOURNAL OF SIGNAL PROCESSING systems FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第2期50卷 115-136页

作者： Wen, Ye Gurun, Selim Chohan, Navraj Wolski, Rich Krintz, Chandra Univ Calif Santa Barbara Santa Barbara CA 93106 USA

simulation is an important tool to study and analyze sensor networks. Prior work in sensor network simulation focuses on homogeneous devices. In this paper, we present a system that performs scalable and accurate simulation of a network of heterogeneous sensor devices, including both Stargate intermediate level devices and mote devices. We study accuracy, performance, and scalability of our system. the results show that we can achieve accurate functional behavior for both standalone Stargate simulation and ensemble simulation of a Stargate and motes. For motes, we have less than 4.06% cycle count error for all benchmarks and for Stargate, we have less than 10% error for most benchmarks, and less than 12.5% error for all benchmarks. We also achieve less than 3.6% error for all benchmarks when simulating an ensemble of Stargate and motes. Our system is also more scalable than prior work. We can simulate 160 sensor nodes in real time speed and 2,048 sensor nodes with ten times slowdown on a 16-node cluster.

关键词： simulation sensor network intermediate sensor node scalability

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Mining dynamic document spaces with massively parallel embedded processors

Mining dynamic document spaces with massively parallel embed...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Jacobs, Jan W. M. Dai, Rui Smit, Gerard J. M. Oce Technol BV NL-5900 MA Venlo Netherlands Natl Univ Singapore Design Technol Inst Fac Engn Singapore 119260 Singapore Univ Twente NL-7500 AE Enschede Netherlands

ISBN: (纸本)3540364102

Currently Oce investigates future document management services. One of these services is accessing dynamic document spaces, i.e. improving the access to document spaces which are frequently updated (like newsgroups). this process is rather computational intensive. this paper describes the research conducted on software development for massively parallel processors. A prototype has been built which processes streams of information from specified newsgroups and transforms them into personal information maps. Although this technology does speed up the training part compared to a general purpose processor implementation its real benefits emerges with larger problem dimensions because of the scalable approach.

关键词： Program processors

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Performance improvements in microprocessor systems utilizing a coprocessor data-path

Performance improvements in microprocessor systems utilizing...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Galanis, Michalis D. Dimitroulakos, Gregory Goutis, Costas E. Univ Patras VLSI Design Lab E&CE Dept Rion 26500 Greece

ISBN: (纸本)1424401550

the speedups achieved in a generic microprocessor system by employing a high-performance data-path are presented in this work. the data-path acts as a coprocessor that accelerates computational intensive kernel regions thereby increasing the overall performance. It is composed by Flexible Computational Components (FCCs) that can realize any two-level template of primitive operations. the automated coprocessor synthesis method and its integration to a design flow for executing applications on the system is presented. Analytical exploration in respect to the type of the custom data-path and to the microprocessor architecture is performed. the overall application speedups of eight real-life applications, relative to the software execution on the microprocessor, are estimated using the design flow. these speedups range from 1.75 to 3.95, having an average value of 2.72, while the overhead in circuit area is small. A comparison with another high-performance data-path showed that the proposed coprocessor achieves better performance while having smaller area-time products for the generated data-paths.

关键词： Coprocessor

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Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures

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JOURNAL OF systems ARCHITECTURE 2007年第8期53卷 466-476页

作者： Blume, H. von Sydow, T. Becker, D. Noll, T. G. Rhein Westfal TH Aachen Chair Elect Engn & Comp Syst D-52062 Aachen Germany

the design of appropriate communication architectures for complex systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chip (NoCs). Recently, the application of deterministic and stochastic Petri-Nets (DSPNs) to model on-chip communication has been proven to be an attractive method to evaluate and explore different communication aspects. In this contribution the modeling of basic NoC communication scenarios featuring different processor cores, network topologies and communication schemes is presented. In order to provide a testbed for the verification of modeling results a state-of-the-art FPGA-platform has been utilized. this platform allows to instantiate a soft-core processor network which can be adapted in terms of communication network topologies and communication schemes. It will be shown that DSPN modeling yields good communication performance prediction results at low modeling effort. Different DSPN modeling aspects in terms of accuracy and computational effort are discussed. (c) 2006 Elsevier B.V. All rights reserved.

关键词： deterministic and stochastic Petri-Nets performance modeling NoC SoC on-chip communication

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A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme

A scalable, multi-thread, multi-issue array processor archit...

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6th international workshop on embedded computer systems - architectures, modeling and simulation

作者： Berekovic, Mladen Niggemeier, Tim Delft Univ Technol Delft Netherlands

ISBN: (纸本)3540364102

A scalable, distributed micro-architecture is presented that emphasizes on high performance computing for digital signal processing applications by combining high frequency design techniques with a very high degree of parallel processing on a chip. the architecture is based on a superscalar processor model with out-of-order execution, that supports specialized, complex DSP function units, and simultaneous instruction issue from multiple independent threads (SMT). Consequent application of fine clustering reduces the cycle-time for wire-sensitive building blocks of the processor like the register file and leads to a distributed architecture model, where independent thread processing units, ALUs, registers files and memories are distributed across the chip and communicate with each other by special networks, forming a "network-on-a-chip" (NOC) [1]. the communication protocol is a modified version of Tomasulo's scheme [2], that was extended to eliminate all central control structures for the data flow and to support multithreading. the performance of the architecture is scalable with both the number of function units and the number of thread units without having any impact on the processors cycle-time.

关键词： computer architecture

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