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检索条件"任意字段=6th International Workshop on Embedded Computer Systems - Architectures, Modeling and Simulation"

共 361 条记录，以下是61-70 订阅

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Reliability-aware virtual data center embedding

Reliability-aware virtual data center embedding

引用

international workshop on Reliable Networks Design and modeling (RNDM)

作者： Cheng Zuo Hongfang Yu Vishal Anand Education Ministry of China University of Electronic Science and Technology of China Chengdu China Department of Computer Science The State University of New York Brockport NY USA

Virtual data center (VDC) embedding along with designing for fault tolerance is a key problem that needs to be addressed while designing a data center. In this work we propose a new reliability-aware VDC embedding algorithm RAVDC that embeds VDC onto the physical servers while guaranteeing the reliability requirement of the VDC. the basic idea of this algorithm is to restrict the number of VMs which can be embedded onto the same physical server to guarantee the VDC reliability, and then reduce the bandwidth consumption as well as the energy consumption. We simulate our algorithm and compare it with existing VDC embedding solution using the fat tree topology. the simulation results show that compared with current VDC embedding algorithms, the proposed algorithm can satisfy VDC reliability requirement, and effectively reduce bandwidth consumption of data center by up to 30% without consuming extra energy.

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High Performance simulations of Kernel P systems

High Performance Simulations of Kernel P Systems

引用

IEEE international Conference on High Performance Computing and Communications (HPCC)

作者： Mehmet E. Bakir Savas Konur Marian Gheorghe Ionut Niculescu Florentin Ipate Department of Computer Science University of Sheffield Sheffield UK Department of Computer Science University of Bucharest Bucharest Romania

the paper presents the use of a membrane computing model for specifying a synthetic biology pulse generator example and discusses some simulation results produced by the tools associated with this model and compare their performances. the results show the potential of the simulation approach over the other analysis tools like model checkers.

关键词： Computational modeling Biological system modeling Fires Biomembranes Kernel Synthetic biology Pulse generation

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Modelling and Stochastic simulation of Synthetic Biological Boolean Gates

Modelling and Stochastic Simulation of Synthetic Biological ...

引用

IEEE international Conference on High Performance Computing and Communications (HPCC)

作者： Daven Sanassy Harold Fellermann Natalio Krasnogor Savas Konur Laurentiu M. Mierla Marian Gheorghe Christophe Ladroue Sara Kalvala School of Computing Science Newcastle University Newcastle Upon Tyne UK School of Computer Science University of Sheffield Sheffield UK School of Computer Science University of Warwick Coventry UK

Synthetic Biology aspires to design, compose and engineer biological systems that implement specified behaviour. When designing such systems, hypothesis testing via computational modelling and simulation is vital in order to reduce the need of costly wet lab experiments. As a case study, we discuss the use of computational modelling and stochastic simulation for engineered genetic circuits that implement Boolean AND and OR gates that have been reported in the literature. We present performance analysis results for nine different state-of-the-art stochastic simulation algorithms and analyse the dynamic behaviour of the proposed gates. Stochastic simulations verify the desired functioning of the proposed gate designs.

关键词： Computational modeling Logic gates Biological system modeling Stochastic processes Genetics Mathematical model Integrated circuit modeling

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Analysis of critical node attacks in mobile ad hoc networks

Analysis of critical node attacks in mobile ad hoc networks

引用

international workshop on Reliable Networks Design and modeling (RNDM)

作者： Dongsheng Zhang James P.G. Sterbenz Department of Electrical Engineering and Computer Science The University of Kansas Lawrence KS USA School of Computing and Communications (SCC) and InfoLab21 Lancaster UK

Understanding network behavior under challenges is essential to constructing a resilient and survivable network. Due to the mobility and wireless channel properties, it is more difficult to model and analyze MANETs (mobile ad hoc networks) under various challenges. Previously, we have modeled network attacks based on a priori complete knowledge of network structure and mobility. In this paper, we present the analysis of MANET behavior under random node failures and centrality-based attacks based on real-time topological information, and provide a comparison of network performance under complete information and real-time attacks. In addition, we adapt betweenness and closeness centrality to measure node significance in asymmetric source/sink network scenarios. the ns-3 simulator is used to examine network throughput under various intelligent attacks. By analyzing network topological properties, we provide a theoretical verification of the simulation results.

关键词： Network topology Ad hoc networks Topology Measurement Mobile computing Real-time systems Wireless sensor networks

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SmartMig: A Case for Page Migration and Self-Interleaving for On-Chip Distributed Memory systems

SmartMig: A Case for Page Migration and Self-Interleaving fo...

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IEEE international Conference on High Performance Computing and Communications (HPCC)

作者： Weiwei Fu Mingmin Yuan Tianzhou Chen Qingsong Shi Li Liu Minghui Wu College of Computer Science Zhejiang University Hangzhou Zhejiang P.R. China School of Information Zhejiang Sci-Tech University Hangzhou Zhejiang P.R. China City College Zhejiang University Hangzhou Zhejiang P.R. China

ISBN: (纸本)9781479961245

this paper tries to optimize the placements of data pages, which have a strong impact on system performance. We find that both core-to-memory distance and contention on MCs and interconnects are critical. Migrating pages to their page access center can mini-mize average memory access distance, but may cause serious contention and congestion, necessitating further schemes for load balancing. Based on these observations, we propose a novel runtime mechanism called SmartMig, in which we mi-grate data pages to shorten memory access distance, while employ page self-interleaving to balance the load across the nodes. We propose models and algorithms to decide the fate of candidate pages. simulation results show that SmartMig achieves performance improvements by 26.9% and 21.0% in terms of normalized IPC and average memory access latency, which is a result of significant reduction of core-to memory distance and load in balance.

关键词： System-on-chip Educational institutions Load management Runtime Routing Conferences Load modeling

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modeling and verification of redundancy policies 6

Modeling and verification of redundancy policies

引用

6th international workshop on Model Based Architecting and Construction of embedded systems, ACESMB 2013 - Co-located with ACM/IEEE 16th international Conference on Model Driven Engineering Languages and systems, MoDELS 2013

作者： Chouh, Hamza Callon, Charlotte Jalal, Ghita Boulanger, Frédéric Taha, Safouan Supélec E3S Computer Science Department France

In this paper, we present a metamodel for specifying redundable software and hardware architectures. this metamodel takes into account the constraints on the number of redundant elements, the number of allowed failures, the execution times and allocation constraints. From such a specification, we generate all possible structural configurations. then, we check that each of these configurations can be scheduled. this has been implemented as a tool chain relying on Alloy, SynDEx, and model transformations in Eclipse/EMF. this work allows system architects to explore different hardware and software architectures to implement different redundancy policies. It has been applied on a simple case study from the Ariane V launcher.

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TimeCube: A Manycore embedded Processor with Interference-Agnostic Progress Tracking

TimeCube: A Manycore Embedded Processor with Interference-Ag...

引用

13th international Conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Gupta, Anshuman Sampson, Jack Taylor, Michael Bedford Univ Calif San Diego San Diego CA 92103 USA

ISBN: (纸本)9781479901036

Recently introduced processors such as Tilera's Tile Gx100 and Intel's 48-core SCC have delivered on the promise of high performance per watt in manycore processors, making these architectures ostensibly as attractive for low-power embedded processors as for cloud services. However, these architectures space-multiplex the microarchitectural resources between many threads to increase utilization, which leads to potentially large and varying levels of interference. this decorrelates CPU-time from actual application progress and decreases the ability of traditional software to accurately track and finely control application progress, hindering the adoption of manycore processors in embedded computing. In this paper we propose Progress Time as the counterpart of CPU-time in space-multiplexed systems and show how it can be used to track application progress. We also introduce TimeCube, a manycore embedded processor that uses dynamic execution isolation and shadow performance modeling to provide an accurate online measurement of each application's Progress Time. Our evaluation shows that a 32-core TimeCube processor can track application progress with less than 1% error even in the presence of a 6x average worst-case slowdown. TimeCube also uses Progress Times to perform online architectural resource management that leads to a 36% improvement in throughput compared to existing microarchitectural resource allocation schemes. Overall, the results argue for adding the requisite microarchitectural structures to support Progress Time in manycore chips for embedded systems.

关键词： cloud computing embedded systems interference microprocessor chips multiprocessing systems resource allocation

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Verilog-based simulation of hardware support for Data-flow concurrency on Multicore systems

Verilog-based simulation of hardware support for Data-flow c...

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13th international Conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Matheou, George Evripidou, Paraskevas Univ Cyprus Dept Comp Sci Nicosia Cyprus

ISBN: (纸本)9781479901036

Data-Driven Multithreading (DDM) is a threaded data-flow model that schedules threads for execution based on data availability. DDM is utilizing a thread Scheduling Unit (TSU) for the management of the threads on sequential processors. In this work we present the hardware implementation of the TSU with synthesizable code using the Verilog HDL and its evaluation using the ISim simulator. the evaluation results show that the TSU is able to run at a maximum frequency of 180 MHz and consumes only 5% of the Xilinx Virtex-6 FPGA resources. the initial results obtained in this work will enable us to design an FPGA based DDM multicore chip consisting of several Microblaze cores driven by the TSU. thus, we will be able to evaluate the performance of the novel threaded data-flow model and have direct comparison with the sequential model on the same hardware.

关键词： data flow computing field programmable gate arrays hardware description languages integrated circuit design microprocessor chips multiprocessing systems performance evaluation processor scheduling

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RAPIDO 2013 - Proc. of the 2013 workshop on Rapid simulation and Performance Evaluation: Methods and Tools, in Conj. with the 8th Intl. Conf. on High-Performance and embedded architectures and Compilers, HiPEAC 2013

RAPIDO 2013 - Proc. of the 2013 Workshop on Rapid Simulation...

引用

2013 4th workshop on Rapid simulation and Performance Evaluation: Methods and Tools, RAPIDO 2013 - In Conjunction with the 8th Intl. Conference on High-Performance and embedded architectures and Compilers, HiPEAC 2013

ISBN: (纸本)9781450315395

the proceedings contain 6 papers. the topics discussed include: Simsys: a performance simulation framework;network-on-chip traffic modeling for data flow applications;exploring alternative flexible OpenCL (FlexCL) core designs in FPGA-based MPSoC systems;prototyping hardware support for irregular applications;TLM modelling of 3D stacked wide I/O DRAM subsystems;and using the CASM language for simulator synthesis and model verification.

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Mapping of PRP/HSR redundancy protocols onto a configurable FPGA/CPU based architecture

Mapping of PRP/HSR redundancy protocols onto a configurable ...

引用

2013 13th international Conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2013

作者： Flatt, Holger Jasperneite, Jürgen Dennstedt, Daniel Hung, Tran Dinh Fraunhofer IOSB-INA Application Center Industrial Automation Langenbruch 6 332657 Lemgo Germany Yacoub Automation GmbH Gustav Meyer Allee 25 13355 Berlin Germany

ISBN: (纸本)9781479901036

this paper presents the mapping of the seamless redundancy protocols PRP and HSR in combination with IEEE 1588 based clock synchronization onto a configurable CPU/FPGA based Redundancy Box architecture. Whereas core functions of PRP, HSR, and IEEE 1588 are mapped onto the FPGA, a CPU executes the control parts of these protocols. An optional attached standard switch ASIC provides direct connection to several network devices. For validation purpose, a special embedded platform is proposed that is composed of an FPGA and a commercial off-the-shelf switch ASIC. the results show that even a low-cost Altera Cyclone IV FPGA comprising 74,000 logic elements fulfills the requirements for protocol processing at 100 Mbps per port. Minimum size frames are forwarded by the FPGA up to two times faster than competitive implementations. three connected PRP/HSR RedBoxes and an IEEE 1588 clock master are synchronizing in laboratory within an accuracy of 30 ns. Using several RedBoxes in PRP and HSR mode, a seamless redundancy is demonstrated for a PROFINET RT test network and supplemental network components. Overall, the presented RedBox can be flexibly integrated into time-synchronized industrial networks in order to significantly increase the communication reliability. © 2013 IEEE.

关键词： Field programmable gate arrays (FPGA)

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