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5th international workshop on embedded computer systems - architectures, modeling,, and simulation

作者： Kim, S Hongik Univ Sch Informat & Comp Engn Seoul South Korea

ISBN: (纸本)354026969X

Pattern matching is one of critical parts of Network Intrusion Detection systems (NIDS). Pattern matching is computationally intensive. To handle an increasing number of attack signature patterns, a NIDS require a multi-pattern matching method that can meet the line-speed of packet transfer. the multi-pattern matching method should efficiently handle a large number of patterns with a wide range of pattern lengths and noncase-sensitive pattern matches. It should also be able to process multiple input characters in parallel. In this paper, we propose a multi-pattern matching hardware accelerator based on Shift-OR pattern matching algorithm. We evaluate the performance of the pattern matching accelerator under various assumptions. the performance evaluation shows that the pattern matching accelerator can be more than 80 times faster than the fastest software multi-pattern matching method used in Snort, a widely used open-source NIDS.

关键词： Pattern matching

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LASSO: A grid-enabled simulation optimization framework 05

LASSO: A grid-enabled simulation optimization framework

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6th international workshop on Grid Computing

作者： Tryby, M Mirghani, B Ranjithan, R Mahithakumar, K Baessler, D Karonis, N N Carolina State Univ Dept Civil Engn Raleigh NC 27695 USA

ISBN: (纸本)0780394925

In this paper, we report our experiences developing a grid-enabled framework for solving environmental inverse problems. the solution approach taken here couples environmental simulation models with global search methods and requires the readily available computational resources of the grid for computational tractability. We present a set of results for a ground water release history reconstruction problem, and report significant performance improvements observed for a deployment of the application on the TeraGrid.

关键词： Grid computing Inverse problems Computational modeling computer architecture computer networks Distributed computing Large-scale systems Mathematical model Design engineering Design optimization

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Sandbridge software tools

Sandbridge software tools

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5th international workshop on embedded computer systems - architectures, modeling, and simulation

作者： Glossner, J Dorward, S Jinturkar, S Moudgill, M Hokenek, E Schulte, M Vassiliadis, S Sandbridge Technol White Plains NY 10512 USA Univ Wisconsin Dept ECE Madison WI 53706 USA Delft Univ Technol Comp Engn Lab Delft Netherlands

ISBN: (纸本)354026969X

We describe the generation of the simulation environment for the Sandbridge Sandblaster multithreaded processor. the processor model is described using the Sandblaster architecture Description Language (SaDL), which is implemented as python objects. Specific processor implementations of the simulation environment are generated by calling the python objects. Using just-in-time compiler technology, we dynamically compile an executing program and processor model to a target platform, providing fast interactive responses with accelerated simulation capability. Using this approach, we simulate up to 100 million instructions per second on a 1 GHz Pentium processor. this allows the system programmer to prototype many applications in real-time within the simulation environment, providing a dramatic increase in productivity and allowing flexible hardware-software trade-offs.

关键词： computer aided software engineering

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embedded computer systems: architectures, modeling, and simulation 1

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丛书名： Lecture Notes in computer Science

1000年

ISBN: (数字)9783540705505

ISBN: (纸本)9783540705499

this book constitutes the refereed proceedings of the 8th international workshop on systems, architectures, modeling, and simulation, SAMOS 2008, held in Samos, Greece, in July 2008. the 24 revised full papers presented together with a contamplative keynote and additional papers of two special workshop sessions were carefully reviewed and selected from 62 submissions. the papers are organized in topical sections on architecture, new frontiers, SoC, application specific contributions, system level design for heterogeneous systems, programming multicores, sensors and sensor networks; and systems modeling and design.

关键词： computer System Implementation computer Communication Networks theory of Computation computer Hardware Processor architectures System Performance and Evaluation

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Exploiting intra-function correlation with the global history stack

Exploiting intra-function correlation with the global histor...

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5th international workshop on embedded computer systems - architectures, modeling, and simulation

作者： Gao, F Sair, S N Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27695 USA

ISBN: (纸本)354026969X

the demand for more computation power in high-end embedded systems has put embedded processors on parallel evolution track as the RISC processors. Caches and deeper pipelines are standard features on recent embedded microprocessors. As a result of this, some of the performance penalties associated with branch instructions in RISC processors are becoming more prevalent in these processors, As is the case in RISC architectures, designers have turned to dynamic branch prediction to alleviate this problem. Global correlating branch predictors take advantage of the influence past branches have on future ones. the conditional branch outcomes are recorded in a global history register (GHR). Based on the hypothesis that most correlation is among intra-function branches, we provide a detailed analysis of the Global History Stack (GHS) in this paper. the GHS saves the global history in the return address stack when a call instruction is executed. Following the subsequent return, the history is restored from the stack. In addition, to preserve the correlation between the callee branches and the caller branches following the call instruction, we save a few of the history bits coming from the end of the callee's execution. We also investigate saving the GHR of a function in the Branch Target Buffer (BTB) when it returns so that it can be restored when that function is called again. Our results show that these techniques improve the accuracy of several global history based prediction schemes by 4% on average. Consequently, performance improvements as high as 13% are attained.

关键词： embedded systems

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Benchmarking mesh and hierarchical bus networks in system-on-chip context

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JOURNAL OF systems ARCHITECTURE 2007年第8期53卷 477-488页

作者： Salminen, Erno Kangas, Tero Lahtinen, Vesa Riihimaki, Jouni Kuusilinna, Kimmo Hamalainen, Timo D. Nokia Technol Platforms Tampere Finland Nokia Res Ctr Tampere Finland

the performance and area of a System-on-Chip depend on the utilized communication method. this paper presents simulation-based comparison of generic, synthesizable single bus, hierarchical bus, and 2-dimensional mesh on-chip networks. Performance of the network depends heavily on the application and therefore six test cases with multiple parameter values are used. Furthermore, two versions of each network topology are compared. the results show that hierarchical bus scales well to large number of agents and offers a good performance and area trade-off although it has smaller aggregate bandwidth and area than mesh. Hierarchical HIBI bus achieves runtimes comparable to 2-dimensional cut-through mesh with about 50% smaller network logic. However, depending on the test case, the runtime can be reduced by 20-50% when wider bus links are utilized. (c) 2006 Published by Elsevier B.V.

关键词： on-chip network simulation benchmark hierarchical bus mesh

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Performance and energy consumption improvements in microprocessor systems utilizing a coprocessor data-path

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JOURNAL OF SIGNAL PROCESSING systems FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第2期50卷 179-200页

作者： Galanis, Michalis D. Dimitroulakos, Gregory Goutis, Costas E. Univ Patras ECE Dept VLSI Design Lab Patras 26500 Achaia Greece

the speedups and the energy reductions achieved in a generic single-chip microprocessor system by employing a high-performance data-path are presented. the data-path acts as a coprocessor that accelerates computational intensive kernel sections thereby increasing the overall performance. the authors have previously introduced the data-path which is composed by flexible computational components (FCCs). these components can realize any two-level sequence of primitive operations. the automated coprocessor synthesis method from high-level software description and its integration to a design flow for executing applications on the system is presented. the overall application speedups of eleven real-life applications, relative to the software execution on the microprocessor, are estimated using the design flow. these speedups are close to theoretical bounds and range from 1.78 to 5.84, having an average value of 3.04, while the overhead in circuit area is small. the energy savings range from 41 to 74%, while the reduction in the application energy-delay product has an average value of 80%. A comparison with another high-performance data-path showed that the proposed coprocessor achieves better performance, consumes less energy and has smaller area-time products for the generated data-paths. Additionally, the FCC data-path achieves better performance in accelerating kernels relative to a VLIW DSP core.

关键词： performance improvements energy reductions coprocessor data-path architectural synthesis design flow template units kernels

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Development of the p-medicine Oncosimulator as a Parallel Treatment Support System 6

Development of the p-medicine Oncosimulator as a Parallel Tr...

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2014 6th international Advanced Research workshop on In Silico Oncology and Cancer Investigation (IARWISOCI)

作者： Blazewicz, Marek Georgiadi, Eleni Ch. Pukacki, Juliusz Stamatakos, Georgios S. Poznan Supercomp & Networking Ctr Applicat Dept Poznan Poland Poznan Univ Tech Poznan Poland Natl Tech Univ Athens Sch Elect & Comp Engn Inst Commun & Comp Syst In Silico Oncol & In Silico Med Grp Athens Greece

ISBN: (纸本)9781479998852

the purpose of this research was the parallelization of the Wilms' Oncosimulator, an integrated cancer treatment support system modeling the growth of nephroblastoma tumors and their in vivo response to chemotherapeutic modalities. In this concept, the Oncosimulator has been optimized in order to perform efficient computations on the newest heterogeneous parallel architectures: the CPU and GPU based computing architectures. the simulator has been implemented using a novel solution for distributed computing on heterogeneous architectures - the Cactus computational toolkit with CaKernel as the module for the computations performed on computing accelerators. In this pUblication the challenges faced during the process of porting the Oncosimulator onto the aforementioned architectures (within CaKernel framework) are addressed, and the performance benefits of such approaches are analyzed. the successful parallelization of the Oncosimulator advances its computational efficiency and enhances its reusability as well as its eventual translation into clinical practice. the research was performed in the context of the p-medicine project*.

关键词： cancer computer architecture hybrid simulation medical computing operating system kernels patient treatment tumours CPU based computing architecture CaKernel framework Cactus computational toolkit GPU based computing architectures Wilms' oncosimulator parallelization aforementioned architectures cancer treatment support system chemotherapeutic modalities computational oncosimulator efficiency computing accelerators heterogeneous parallel architectures in vivo response nephroblastoma tumor growth p-medicine oncosimulator development Acceleration Biomedical imaging computer architecture Europe Graphics processing units Programmable logic arrays Vectors computer Architecture operating system kernels medical computing Biomedical imaging hybrid simulation patient treatment Cancer Graphics Processing Unit Tumours acceleration programmable logic arrays Support systems parallelization

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Tuning a protocol processor architecture towards DSP operations

Tuning a protocol processor architecture towards DSP operati...

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5th international workshop on embedded computer systems - architectures, modeling,, and simulation

作者： Paakkulainen, J Virtanen, S Isoaho, J Univ Turku Dept Informat Technol FIN-20520 Turku Finland Turku Ctr Comp Sci Embedded Syst Lab FIN-20520 Turku Finland

ISBN: (纸本)354026969X

In this paper we present an experiment in enhancing our transport triggered protocol processor hardware platform to support DSP applications. Our focus is on integrating support for both application domains into a single processor without loss of performance in either domain. Such a processor could be taken advantage of. in applications like Voice-over-IP communication using hand-held devices, where functionality is needed from both domains. As our first step in bridging the gap between the protocol processing and DSP domains we implement support for FIR filtering. We analyze four different architectural instances for implementing FIR filters according to their performance and bus utilisation. We were able to determine that protocol processing and DSP operations can be executed in parallel very efficiently. the implementations were verified with VHDL simulations and synthesis using 0.18 mu m CMOS technology.

关键词： Program processors

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Relaxed Subgraph Execution Model for the throughput Evaluation of IBSDF Graphs 17

Relaxed Subgraph Execution Model for the Throughput Evaluati...

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17th Annual international Conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Deroui, Hamza Desnos, Karol Nezan, Jean-Francois Munier-Kordon, Alix IETR INSA Rennes CNRS UMR 6164 Rennes France Sorbonne Univ UPMC UMR 7606 LIP6 Paris France

ISBN: (纸本)9781538634370

the Interface-Based Synchronous Dataflow (IBSDF) Model of Computation (MoC) is a hierarchical extension of the well-known Synchronous Dataflow (SDF) MoC. the IBSDF model extends the semantics of the SDF model by introducing a graph composition mechanism based on hierarchical interfaces. the IBSDF model introduces also execution rules to ease the analysis of the IBSDF graph such as evaluating the throughput;an essential key performance to evaluate when designing Digital Signal Processing (DSP) systems. However, respecting the execution rules may slow down the execution of IBSDF graphs, and so stop the applications to reach their maximum throughput. this article presents first how to speed-up the execution of an IBSDF graph by relaxing the execution rules. Second, a new method to compute the throughput of IBSDF graphs under a relaxed execution. Finally, a performance comparison between the proposed method and basic methods that rely on a transformation of the IBSDF graph to an equivalent non-hierarchical graph of potentially exponential size. the proposed method outperforms basic methods and makes it possible to evaluate the maximum throughput of large IBSDF graphs in less than 2 seconds.

关键词： throughput Schedules Computational modeling Programming Production Electronic mail Analytical models

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