作者：
Radmer, JochenKrüger, Jörg
Technische Universität Berlin Berlin Germany
Fraunhofer Gesellschaft Berlin Germany
For man-machine cooperation the detection of pose changes appearing as object motion is a crucial factor. Preveous approaches were based on luminance and chrominance data used for subsequent pose information extractio...
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ISBN:
(纸本)9780889866911
For man-machine cooperation the detection of pose changes appearing as object motion is a crucial factor. Preveous approaches were based on luminance and chrominance data used for subsequent pose information extraction. In contrast we present an algorithm for the detection of moving objects for dynamic 21/2D data providing direct spatial information based on the non-parametric model approach proposed by Elgammal [3]. the data is obtained by a range camera of static pose viewing the scene. Giving the coarse data captured by the camera the algorithm takes advantage of the dynamic and spatial characteristics of the data by evaluating temporal variation distribution. To counter long time changes, iterative updating of the used background model is performed by a selective updating approach utilizing the probability estimate.
this paper discusses the novel application of an idea rooted in cognitive psychology to face recognition (FR). this cognitive-psychology method adapted for FR is evaluated against the difficult problem of ageprogressi...
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ISBN:
(纸本)9780889866911
this paper discusses the novel application of an idea rooted in cognitive psychology to face recognition (FR). this cognitive-psychology method adapted for FR is evaluated against the difficult problem of ageprogression. the age-progression problem occurs when enrolled images used by the FR algorithm are younger, typically more than one year in difference, than the test (probe) image. A model of a phenomenon in cognitive psychology known as "own-race bias" (ORB) is employed using Principle Components Analysis (PCA) as the face recognition engine. the ORB FR system has demonstrated performance gain of 200% over the baseline technique of Eigenfaces on the MORPH Album 2 face database. Where the baseline system Eigen face FR (which has been described in [1]) had a rank-based identification rate of 23%, the ORB-based FR achieved rates in the mid 50%.
this paper presents the new approach to parallel calculations withthe use of mixed formats. Usually parallel computations are done in multibit Pulse Code Modulation (PCM). Using this format requires doing multibit mu...
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ISBN:
(纸本)9780889866560
this paper presents the new approach to parallel calculations withthe use of mixed formats. Usually parallel computations are done in multibit Pulse Code Modulation (PCM). Using this format requires doing multibit multiplications what often decreases the speed of calculations. Mixed formats, which join differential modulation codes such as Delta Modulation (DM) with PCM, can lead to the decrease of code word length and speed-up operation in DSP (Digital Signal Processing). Some kinds of DM such as MDPCM-PCM (Modified Differential Pulse Code Modulation) and SDPCM-PCM (Synthetic DPCM) enable to replace the time-consuming multiplications with fast shift operations. the purpose of this work is working out the new processing methods for the fast-acting increase of DSP algorithms on the basis of parallel computations in mixed formats, especially withthe use of MDPCM-PCM and SDPCM-PCM formats.
international Federation for Information Processing the IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. the scope of the series includes: foundations o...
ISBN:
(数字)9780387754949
ISBN:
(纸本)9780387754932
international Federation for Information Processing the IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. the scope of the series includes: foundations of computerscience; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of referred internationalconferences in computerscience and interdisciplinary fields are featured. these results often precede journal publication and represent the most current research. the principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing. For more information about the 300 other books in the IFIP series, please visit ***.
international Federation for Information Processing the IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. the scope of the series includes: foundations o...
ISBN:
(数字)9780387754666
ISBN:
(纸本)9780387754659
international Federation for Information Processing the IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. the scope of the series includes: foundations of computerscience; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of referred internationalconferences in computerscience and interdisciplinary fields are featured. these results often precede journal publication and represent the most current research. the principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing. For more information about the 300 other books in the IFIP series, please visit ***.
Aggressive execution-path-based compiler and architecture optimizations require a path profiler that can specify several hottest paths at low overheads. Based on our observation that a limited number of paths are exec...
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ISBN:
(纸本)9780889866560
Aggressive execution-path-based compiler and architecture optimizations require a path profiler that can specify several hottest paths at low overheads. Based on our observation that a limited number of paths are executed frequently in hot loops, we have designed a two-level hot path detector to specify such hottest paths within hot loops. the detector consists of two tables: a filter table and an accumulator table. the filter table captures the behavior of locally hot paths. this hot path information is then sent to the accumulator table to capture the behavior of globally hot paths. the path profiler also provides us withthe information on hot loops as well as problematic instructions contained in the hot paths. they may be effectively utilized for the optimizations. We evaluate the profiler using SPEC CINT2000. the results show that the two-level organization has an effect of filtering out less frequent paths, and that the top 5 frequent paths and their order can be adequately detected.
We have developed a software system that can translate sequential binary codes to the multithreaded ones at the binary code level. this system parallelizes frequently executed loops within programs to improve the perf...
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ISBN:
(纸本)9780889866560
We have developed a software system that can translate sequential binary codes to the multithreaded ones at the binary code level. this system parallelizes frequently executed loops within programs to improve the performance by exploiting loop-level parallelism for numerical application programs. However, many loops within non-numerical application programs are hard to be parallelized because of their small amount of loop-level parallelism and complex program structures, and it is difficult to attain speedup by exploiting loop-level parallelism. therefore, it is necessary to generate multithreaded codes, taking more general program structure than loop structure within program into consideration. In this paper, we propose a thread partitioning technique of multithreaded execution along a hot path (the most frequently executed control sequence of basic blocks), taking more general program structure than loops into consideration. And we apply the proposed technique to three non-numerical application programs of SPEC CINT95 benchmark, and evaluate the performance improvement by simulation. the evaluation result shows that the proposed technique can improve the performance of non-numerical application program, whose performance cannot be improved by exploiting loop-level parallelism.
Withthe rapid advances in computerscience and technology, critical computer-based systems, such as those in aerospace, military, and power industries exhibit more complex dependent and dynamic behaviors, which canno...
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ISBN:
(纸本)9780889867055
Withthe rapid advances in computerscience and technology, critical computer-based systems, such as those in aerospace, military, and power industries exhibit more complex dependent and dynamic behaviors, which cannot be fully captured by existing reliability modeling tools. In this paper, we introduce a new reliability modeling tool, called dynamic reliability block diagrams (DRBD), for modeling dynamic relationships between components, such as state dependency and redundancy. We give formal semantics for some key DRBD constructs using Object-Z formalism. In order to verify and validate the correctness of a DRBD model, we propose to convert a DRBD model into a colored Petri net (CPN), and use an existing Petri net tool, called CPN Tools, to analyze and verify dynamic system behavioral properties. Our case study and experimental results show that DRBD provides a powerful tool for system reliability modeling, and our proposed verification approach can effectively ensure the correct design of DRBD reliability models for complex and large-scale computer-based systems.
Network processors (NPs) are designed to provide both performance and flexibility through the implementation of both parallel and programmable architectures. Typically, such processors encompass a parallel processor c...
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ISBN:
(纸本)9780889867048
Network processors (NPs) are designed to provide both performance and flexibility through the implementation of both parallel and programmable architectures. Typically, such processors encompass a parallel processor core with several memories and specialized co-processors. A common task performed by such processors is packet processing that is both complex and highly repetitive. Consequently, the challenge is to define an on-chip network processor architecture that is capable of meeting the performance requirements of packet processing. Withthe current technological advances, it is expected that many (network) processor cores are to be incorporated onto the same chip to perform packet processing for which an efficient configuration must be determined. In this paper, we propose a general framework for analyzing the performance of a network processor that consists of an (on-chip) network of NPs. For this purpose, we utilize queuing theory to model the proposed network processor and analyze it. More specifically, the Jackson network model is utilized to represent our network processor. the simulation results show that the proposed network processor is able to improve the response time and throughput when compared to a more traditional network processor.
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