parallelization of optimization routines is now increasingly resorted to, because of the heavy computation associated withthe optimization of electromagnetic products in the process of their design. this paper evalua...
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parallelization of optimization routines is now increasingly resorted to, because of the heavy computation associated withthe optimization of electromagnetic products in the process of their design. this paper evaluated the possibilities for parallelization in electromagnetic product design. the several optimization algorithms available are evaluated for their parallelizability. It is further shown that, given the present limits of technology in relation to the number of processors available on shared memory computers of parallel architecture, parallelization in electromagnetic optimization is not necessarily worth attempting at present. thus, works of this nature, area of necessity, for the future, in readiness for that day when a new generation of parallel computer is available to us.
this paper presents a parallel architecture that can simultaneously perform block-matching motion estimation (ME) and discrete cosine transform (DCT). Because DCT and ME are both processed block by block, it is prefer...
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ISBN:
(纸本)9783540729044
this paper presents a parallel architecture that can simultaneously perform block-matching motion estimation (ME) and discrete cosine transform (DCT). Because DCT and ME are both processed block by block, it is preferable to put them in one module for resource sharing. Simulation results performed using Simulink demonstrate that the parallel fashioned architecture improves the performance in terms of running time by 18.6% compared to the conventional sequential fashioned architecture.
ADAS (Advanced Driver Assistance Systems) algorithms increasingly use heavy image processing operations. To embed this type of algorithms, semiconductor companies offer many heterogeneous architectures. these SoCs (Sy...
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ISBN:
(纸本)9781479989379
ADAS (Advanced Driver Assistance Systems) algorithms increasingly use heavy image processing operations. To embed this type of algorithms, semiconductor companies offer many heterogeneous architectures. these SoCs (System on Chip) are composed of different processing units, with different capabilities, and often with massively parallel computing unit. Due to the complexity of these SoCs, predicting if a given algorithm can be executed in real time on a given architecture is not trivial. In fact it is not a simple task for automotive industry actors to choose the most suited heterogeneous SoC for a given application. Moreover, embedding complex algorithms on these systems remains a difficult task due to heterogeneity, it is not easy to decide how to allocate parts of a given algorithm on the different computing units of a given SoC. In order to help automotive industry in embedding algorithms on heterogeneous architectures, we propose a novel approach to predict performances of image processingalgorithms applicable on different types of computing units. Our methodology is able to predict a more or less wide interval of execution time with a degree of confidence using only high level description of algorithms, and a few characteristics of computing units.
We explore three commodity parallelarchitectures: multi-core CPUs, the Cell BE processor, and graphics processing units. We have implemented four algorithms on these three architectures: solving the heat equation, in...
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ISBN:
(纸本)9783642116193
We explore three commodity parallelarchitectures: multi-core CPUs, the Cell BE processor, and graphics processing units. We have implemented four algorithms on these three architectures: solving the heat equation, inpainting using the heat equation, computing the Mandelbrot set, and MJPEG movie compression. We use these four algorithms to exemplify the benefits and drawbacks of each parallel architecture.
A language for semi-structured documents, XML has emerged as the core of the web services architecture, and is playing crucial roles in messaging systems, databases, and document processing. However, the processing of...
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ISBN:
(纸本)9781424403431
A language for semi-structured documents, XML has emerged as the core of the web services architecture, and is playing crucial roles in messaging systems, databases, and document processing. However, the processing of XML documents has a reputation for poor performance, and a number of optimizations have been developed to address this performance problem from different perspectives, none of which have been entirely satisfactory. In this paper, we present a seemingly quixotic, but novel approach: parallel XML parsing. parallel XML parsing leverages the growing prevalence of multicore architectures in all sectors of the computer market, and yields significant performance improvements. this paper presents our design and implementation of parallel XML parsing. Our design consists of an initial preparsing phase to determine the structure of the XML document, followed by a full, parallel parse. the results of the preparsing phase are used to help partition the XML document for data parallelprocessing. Our parallel parsing phase is a modification of the libxml2 [1] XML parser, which shows that our approach applies to real-world, production quality parsers. Our empirical study shows our parallel XML parsing algorithm can improved the XML parsing performance significantly and scales well.
As current reasoning techniques are not designed for massive parallelisation, usage of parallel computation techniques in reasoning establishes a major research problem. I will propose two possibilities of applying pa...
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ISBN:
(纸本)9783540885634
As current reasoning techniques are not designed for massive parallelisation, usage of parallel computation techniques in reasoning establishes a major research problem. I will propose two possibilities of applying parallel computation techniques to ontology reasoning: parallelprocessing of independent ontological modules, and tailoring the reasoning algorithms to parallelarchitectures.
Window-based parallelarchitectures are here considered as target structures for the computation of low and medium level image processingalgorithms. their definition stems from a general reformulation of algorithms, ...
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作者：
El Baz, D.CNRS
LAAS 7Ave Colonel Roche F-31077 Toulouse 4 France
the implementation of parallel asynchronous iterative algorithms on message passing architectures is considered. Several issues related to communication via message passing interfaces or libraries such as MPI-1, MPI-2...
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ISBN:
(纸本)9780769527840
the implementation of parallel asynchronous iterative algorithms on message passing architectures is considered. Several issues related to communication via message passing interfaces or libraries such as MPI-1, MPI-2, PVM or SHMEM are discussed in this survey paper Practical impleinentations are proposed.
Image processingalgorithms are widely used in the automotive field for ADAS (Advanced Driver Assistance System) purposes. To embed these algorithms, semiconductor companies offer heterogeneous architectures which are...
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ISBN:
(纸本)9781467375894
Image processingalgorithms are widely used in the automotive field for ADAS (Advanced Driver Assistance System) purposes. To embed these algorithms, semiconductor companies offer heterogeneous architectures which are composed of different processing units, often with massively parallel computing unit. However, embedding complex algorithms on these SoCs (System on Chip) remains a difficult task due to heterogeneity, it is not easy to decide how to allocate parts of a given algorithm on processing units of a given SoC. In order to help automotive industry in embedding algorithms on heterogeneous architectures, we propose a novel approach to predict performances of image processingalgorithms on different computing units of a given heterogeneous SoC. Our methodology is able to predict a more or less wide interval of execution time with a degree of confidence using only high level description of algorithms to embed, and a few characteristics of computing units.
Low latency image processing and high FPS (frames per second) is significant for high resolution decision making in many object recognition applications. Reading frames in between processing of a video is too slow and...
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ISBN:
(纸本)9781538651636
Low latency image processing and high FPS (frames per second) is significant for high resolution decision making in many object recognition applications. Reading frames in between processing of a video is too slow and sluggish as the corresponding reading and decoding the frames are done in the main processingthread. Packages, such as imutils provide such off-the-shelf image processingalgorithms which apply multi-threading to achieve low latency. However, the algorithms are unable to perform computationally expensive image processing operations. In this paper, we apply a parallelprocessing technique based on co-incident multi-threading to decrease the latency for computationally expensive cases. the technique is evaluated using a prototype of smart car to show that FPS rate is increased and time complexity of algorithms is reduced by an order of n.
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