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检索条件"任意字段=7th International Conference on Algorithms and Architectures for Parallel Processing"

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A fast pansharpening method based on object-space-consistency and GPU parallel processing 7

A fast pansharpening method based on object-space-consistenc...

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7th international conference on Advanced Electronic Materials, Computers, and Software Engineering, AEMCSE 2024

作者： Xu, Mingyuan Zhang, Xueqi Cai, Zhengyang Hubei University of Technology No. 28 Nanli Road Hongshan District Wuhan430068 China

ISBN: (纸本)9781510681866

the fusion of panchromatic and multispectral images is a prerequisite for obtaining multispectral images with high spatial resolution (HRMS). the traditional data processing mode requires that the acquired panchromatic data and multispectral data be transmitted to the ground through the star-ground link, and then a series of correction, registration and fusion operations are conducted in order to obtain HRMS. this processing mode has low timeliness and cannot meet the demand of on-board real-time processing. To solve this problem, we perform efficient registration and fusion processing for the images containing the target region acquired in real time during satellite orbit. Specifically, we propose a fast virtualized registration method based on object-space-consistency, which is capable of obtaining accurately registered images under the premise of ensuring real-time performance. On this basis, we utilize GPU acceleration to parallelize the time-consuming steps of the traditional fusion algorithm, thereby achieving rapid fusion processing while guaranteeing the fusion performance. through experiments on an on-board simulation system, our method has been able to achieve 15.10 times speedup compared to the traditional registration and fusion processing while guaranteeing good performance. © 2024 SPIE.

关键词： Image fusion

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A Multiplierless parallel Digital Down Converter for High Resolution Spaceborne SAR 7

A Multiplierless Parallel Digital Down Converter for High Re...

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7th international conference on Intelligent Computing and Signal processing, ICSP 2022

作者： Sun, Jia Hou, Ruohan Dang, Hongxing Xi'an China

ISBN: (纸本)9781665478571

High resolution spaceborne SAR has unique advantages in target recognition and earthquake rescue due to its refined description of target characteristics. the resolution is developing from the meter level to the decimeter level, which brings a huge increase in signal bandwidth. the traditional analog demodulation or serial digital down-conversion processing methods are no longer suitable for the needs. In addition, the limited scale of the onboard digital processing chip makes it impossible to simply copy the serial processing into a multichannel parallel mode. In this paper, a novel digital down converter is designed according to the band-pass sampling theorem and the fast finite impulse response algorithm (FFA) combined with the characteristics of the spaceborne digital processing chip. Compared with the traditional method, the resource consumption of the proposed method is obviously improved. With the increase of the signal bandwidth, this advantage is more obvious. the proposed method is suitable for high-resolution spaceborne SAR, large bandwidth millimeter wave radar, etc. © 2022 IEEE.

关键词： Synthetic aperture radar

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parallel integer multiplication 30

Parallel integer multiplication

引用

30th Euromicro international conference on parallel, Distributed and Network-Based processing (PDP)

作者： Samuel, Vivien PSL Res Univ CNRS Ecole Normale Super Dept Informat ENS 45 Rue Ulm Paris France Univ Lorraine CNRS INRIA LORIA Nancy France

ISBN: (纸本)9781665469586

Multiplication is a fundamental step in many algorithms. If the multiplication of two integers of n words has a complexity of M(n), divisions and squares can be computed in O(M(n)) as well and the greatest common divisor can be computed in O(M(n) log n). thus being able to have a small value for M(n) is extremely important. To this day, the best known algorithm for reachable values is the Schonhage-Strassen algorithm which is implemented by a few arithmetic libraries. Asymptotically faster algorithms exist, however no computer is able to hold numbers big enough for those algorithms to outrun Schonhage-Strasser. the GNU Multiple Precision (GMP) library has a sequential-only implementation of Schonhage-Strassen. However some algorithms contains a step which is a single big multiplication. thus when trying to parallelize such an algorithm, one requires a parallel algorithm for multiplication. An example of such an algorithm is the batch factorization for Number Field Sieve. thus people trying to implement a parallel version of such algorithms need to find an arithmetic library that implements a parallel integer multiplication. An example of such a library is the Flint (Fast Library for Number theory) library that contains a parallel implementation of Schonhage-Strassen. In this article we present an implementation of Schonhage-Strassen, that reaches a speedup of 20 for the multiplication of two integers of 10(7) words of 64 bits using a Xeon Gold with 32 cores.

关键词： Gold Codes Libraries Complexity theory parallel algorithms Arithmetic

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A Review of FPGA-based Graph Neural Network Accelerator architectures 24

A Review of FPGA-based Graph Neural Network Accelerator Arch...

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7th international conference on Signal processing and Machine Learning, SPML 2024

作者： Zhang, Xiaojun Xia, Yongwang Kang, Ziyang Du, Xiangbao Gao, Jian Shandong University of Science and Technology Qingdao China

ISBN: (纸本)9798400717192

Graph Neural Networks (GNNs) can effectively process graph data and have been widely applied in fields such as drug discovery, social networks, and recommendation systems. With the continuous increase in datasets and the emergence of more advanced GNNs models, improving the inference speed of GNNs has become an urgent need. Field programmable gate array (FPGA) has the characteristics of high parallelism and programmability, which can achieve higher performance and lower power consumption. Using FPGA to design GNNs accelerators offers more advantages over CPU and GPU. However, designing FPGA-based GNNs accelerators still faces many challenges, such as the inability to fully utilize allocated computing resources and the difficulty in achieving a universal GNNs architecture. In this paper, we first summary the challenges that FPGA-based GNNs accelerators need to address. Secondly, we introduce some classic models of GNNs, as well as several frequently-used graph datasets for GNNs accelerators. then, we explain the architectures of GNNs accelerators and analyse their performance. Finally, we discuss the challenges and development directions of FPGA-based GNNs accelerators in the future. © 2024 ACM.

关键词： Graph neural networks

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Fast approximation algorithms for scheduling uniform parallel batch machines with inclusive processing set restriction

Fast approximation algorithms for scheduling uniform paralle...

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Advanced algorithms and Control Engineering (ICAACE), international conference on

作者： Yanyue Liang Lihong Zhang Shuguang Li School of Computer Science and Technology Shandong Technology and Business University Yantai China

ISBN: (数字)9798350361445

ISBN: (纸本)9798350361452

We address the problem on uniform parallel batch machines to minimize makespan where each job is restricted to a specific subset of machines, known as its processing set. Batch machines have diverse speeds and capacities. Each batch machine has the ability to concurrently process multiple jobs as long as the capacity allows. the length of a batch is defined as the largest length of all the jobs contained within it. We present fast approximation algorithms for inclusive processing set.

关键词： Schedules Control engineering Process control Approximation algorithms Scheduling

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Research and Implementation of parallel Optimization of SM3 Algorithm Based on Multithread 7

Research and Implementation of Parallel Optimization of SM3 ...

引用

7th international conference on Intelligent Computing and Signal processing, ICSP 2022

作者： Liu, Yongjie Zhao, Rongcai Han, Lin Xie, Jingming Zhengzhou University School of Information Engineering Zhengzhou450000 China Zhengzhou University National Supercomputing Zhengzhou Center Zhengzhou450000 China

ISBN: (纸本)9781665478571

the national secret SM3 cryptographic hash algorithm is to generate a fixed hash value after iterative compression and expansion of a group of messages, which is mainly suitable for the generation of digital signatures and random verification codes. the algorithm is based on the hash calculation, which is a computationally intensive task with high computational intensity. In order to improve the operating efficiency of the algorithm, make it achieve optimized operating effects on a multi-core system. this article uses multi-threaded parallel to rewrite the algorithm in parallel: through the privatization of variable attributes to avoid memory read and write conflicts in multi-threaded parallel, through dynamic task scheduling to achieve multi-threaded load balancing, so as to realize the parallel version of SM3 algorithm. Experimental results show that the parallel algorithm has a good linear acceleration when the number of threads increases, and the speedup ratio is increased by 2-6 times compared with the serial algorithm, which can provide a reference for the performance improvement of the algorithm on multi-core computing components. © 2022 IEEE.

关键词： Hash functions

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Small Signal Model Design of Full Bridge LC-LC Series parallel Resonant Inverter 7

Small Signal Model Design of Full Bridge LC-LC Series Parall...

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7th international conference on Intelligent Computing and Signal processing, ICSP 2022

作者： Zhang, Bin Hei, Guoyu Chongqing Aerospace Polytechnic School of Electronic Information and Communication Engineering Chongqing400021 China

ISBN: (纸本)9781665478571

this paper mainly studies the dynamic performance of constant frequency phase-shift controlled full bridge LC-LC series parallel resonant inverter, analyzes its small signal model by phasor domain modeling, and obtains the large signal model in phasor domain of resonant inverter by transforming the time domain into phasor domain. then, after adding small signal disturbance, the small signal model in phasor domain can be obtained. On this basis, the loop compensation design is carried out for the large signal and small signal models established by phasor modeling method. Finally, an experimental prototype with an output power of 200W is built. the simulation results verify the correctness of the theoretical analysis and design. © 2022 IEEE.

关键词： Electric inverters

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7th IFIP TC 10 international Embedded Systems Symposium, IESS 2022

7th IFIP TC 10 International Embedded Systems Symposium, IES...

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7th IFIP TC 10 international Embedded Systems Symposium, IESS 2022

ISBN: (纸本)9783031342134

the proceedings contain 12 papers. the special focus in this conference is on international Embedded Systems. the topics include: Synthetic Data for Machine Learning on Embedded Systems in Precision Agriculture;using Network Architecture Search for Optimizing Tensor Compression;simulation of Timing Attacks and Challenges for Early Side-Channel Security Analysis;adaptation for Energy Saving in Time-Triggered Systems Using Meta-scheduling with Sample Points;communication Layer Architecture for a Production Line Digital Twin Using Hierarchical Colored Petri Nets;Exploiting Heterogeneity in PIM architectures for Data-Intensive Applications;Demonstrating Scalability of the Checkerboard GPC with SystemC TLM-2.0;MAFAT: Memory-Aware Fusing and Tiling of Neural Networks for Accelerated Edge Inference;Memristor-only LSTM Acceleration with Non-linear Activation Functions;Minimizing Memory Contention in an APNG Encoder Using a Grid of processing Cells.

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A Collaborative Grouping Aggregation Query Scheme on Heterogeneous Computing Systems 7

A Collaborative Grouping Aggregation Query Scheme on Heterog...

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7th international conference on Cloud Computing and Big Data Analytics, ICCCBDA 2022

作者： Zhou, Kailai Feng, Xinwei College of Software Engineering Zhengzhou University of Light Industry Zhengzhou China

ISBN: (纸本)9781665487115

Aggregation is one of the most common operations in data analytics systems, but complex aggregation query like grouping aggregation on massive data sets is a relatively expensive operation. thus, improving the efficiency of aggregation query has become a hot topic for database researchers. the emergence of massively parallel coprocessors provides a way to solve this issue. Prior works focus mainly on aggregation optimization using one kind of coprocessors, but little is known about the performance impact on the heterogeneous computing system with diverse coprocessors, such as GPGPUs, MICs or FPGAs. To investigate the potential benefits of the use of heterogeneous computing systems in improving the performance of aggregation operation, in this paper, we design a grouping aggregation scheme with GPUs and MICs to work collaboratively. the scheme includes task partitioning method, data transfer mode, and aggregation algorithm optimization. To verify the effectiveness of our collective aggregation scheme, we performed a series of experiments on a heterogeneous platform with one Intel Xeon Phi coprocessor and one NVIDIA GPU coprocessor, and the results have shown that our aggregation processing strategy for the heterogeneous systems is effective and can achieve noticeable performance improvement comparing the CPU-only parallel computing system, even taking the communication overhead via PCI Express bus into account. © 2022 IEEE.

关键词： Microwave integrated circuits Databases Collaboration parallel processing Heterogeneous networks Hardware Partitioning algorithms

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High Performance Scalable Recursive Block Matrix Inverse for Multicore architectures 7

High Performance Scalable Recursive Block Matrix Inverse for...

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7th international conference on parallel, Distributed and Grid Computing, PDGC 2022

作者： Kumar, Mandeep Kaur, Gagandeep Chandigarh University University Institute of Computing Mohali India Locuz Enterprise Solutions Ltd Delhi India

ISBN: (纸本)9781665454018

the inversion of a matrix, which is computationally intensive and involves numerous operations, is extensively used in various scientific and engineering applications. the block matrix inverse formula for n x n matrices requires the inverse of two half-sized matrices and six multiplications between two half-sized matrices. In this work, we proposed high performance scalable recursive block matrix inverse algorithm for multicore architectures based on block matrix inverse that performs recursively and transforms two half-sized matrices into a minimal 2 x 2 matrix inverse. We performed extensive experimental performance evaluation and analysis of recursive block matrix inverse on shared memory multicore system and achieved scalability and throughput (Double Precision GFLOPS) for large matrix inversion. We compared recursive block matrix inverse with MKL LAPACK and found it to be far superior. We proposed a combination of recursive block matrix inverse and MKL LAPACK matrix multiplication routines for multicore architectures, which outperforms MKL LAPACK matrix inverse. © 2022 IEEE.

关键词： Matrix algebra

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