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检索条件"任意字段=7th International Conference on Algorithms and Architectures for Parallel Processing"
2975 条 记 录,以下是101-110 订阅
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Low Latency Image processing of Transportation System Using parallel processing co-incident Multithreading (PPcM)  7
Low Latency Image Processing of Transportation System Using ...
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Joint 7th international conference on Informatics, Electronics & Vision (ICIEV) / 2nd international conference on Imaging, Vision and Pattern Recognition (icIVPR)
作者: Shammi, Sanjana Khan Sultana, Samia Islam, Md Saiful Chakrabarty, Amitabha BRAC Univ Dept Comp Sci & Engn Dhaka Bangladesh
Low latency image processing and high FPS (frames per second) is significant for high resolution decision making in many object recognition applications. Reading frames in between processing of a video is too slow and... 详细信息
来源: 评论
Load balancing in dynamic networks
Load balancing in dynamic networks
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7th international Symposium on parallel architectures, algorithms and Networks (I-SPAN 2004)
作者: Elsässer, R Monien, B Schamberger, S Univ Gesamthsch Paderborn Fak Elektotech Informat & Math D-33102 Paderborn Germany
Efficient load balancing algorithms are the key to many efficient parallel applications. Until now, research in this area mainly focused on static networks. However observations show that diffusive algorithms, origina... 详细信息
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Novel Multi-Layer Network Decomposition Boosting Acceleration of Multi-core algorithms
Novel Multi-Layer Network Decomposition Boosting Acceleratio...
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IEEE 24th international conference on Application-Specific Systems, architectures and Processors (ASAP)
作者: Grivas, Athanasios K. Mak, Terrence Yakovlev, Alex Wray, Jonny Newcastle Univ Sch Elect & Elect Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England
Complex networks are a technique for the modeling and analysis of large data sets in many scientific and engineering disciplines. Due to their excessive size conventional algorithms and single core processors struggle... 详细信息
来源: 评论
Mapping to reduce contention in multiprocessor architectures  7
Mapping to reduce contention in multiprocessor architectures
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7th international parallel processing Symposium, IPPS 1993
作者: Schwiebert, L. Jayasimha, D.N. Dept. of Comput. and Inf. Sci. Ohio State Univ. ColumbusOH43210-1277 United States
Reducing communication overhead has been widely recognized as a requirement for achieving efficient mappings which substantially reduce the execution time of parallel algorithms. this paper presents an iterative heuri... 详细信息
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Performance analysis of interconnection networks under bursty and batch arrival traffic
Performance analysis of interconnection networks under burst...
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7th international conference on algorithms and architectures for parallel processing
作者: Wu, Yulei Min, Geyong Wang, Lan Univ Bradford Dept Comp Sch Informat Bradford BD7 1DP W Yorkshire England
Analytical models for adaptive routing in multicomputer interconnection networks with the traditional non-bursty Poisson traffic have been widely reported in the literature. However, traffic loads generated by many re... 详细信息
来源: 评论
Data interoperation between ChinaGrid and SRB
Data interoperation between ChinaGrid and SRB
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7th international conference on algorithms and architectures for parallel processing
作者: Xiong, Muzhou Jin, Hai Wu, Song Huazhong Univ Sci & Technol Serv Comp Technol Cluster & Grid Comp Lab Sch Comp Sci & Technol Wuhan 430074 Peoples R China
Separated grid systems. are becoming the new information islands when more and more grid systems are deployed. Grid interoperation is a direction to solve that problem. this paper introduces the implementation of data... 详细信息
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Increased throughput and Power Efficient Multi-Path 1024-Point Radix-22 FFT Processor for Signal processing Applications  7
Increased Throughput and Power Efficient Multi-Path 1024-Poi...
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7th international conference on Computing in Engineering and Technology, ICCET 2022
作者: thokala, Mohan Rao Gopi, Telagamalla Department of Electronics and Communication Engineering Siddhartha Institute of Engineering and Technology Telangana State Hyderabad501506 India
FFT processor used for high-speed signal processing applications, such that to meet the required high-speed applications, FFT processor uses pipeline and parallel processing algorithms to provide such high-speed appli... 详细信息
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parallel analog algorithms for processing polygonal images on a systolic screen  7
Parallel analog algorithms for processing polygonal images o...
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7th international parallel processing Symposium, IPPS 1993
作者: Guha, S. Wisconsin-Milwaukee Univ. WI53201 United States
the systolic screen is a very natural parallel architecture for image processing. A square root n∗ square root n systolic screen consists of a square root n∗ square root n mesh-of-processors with each processor repres... 详细信息
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A parallel infrastructure on dynamic EPIC SMT
A parallel infrastructure on dynamic EPIC SMT
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7th international conference on algorithms and architectures for parallel processing
作者: Deng, Qingying Zhang, Minxuan Jiang, Jiang Natl Univ Def Technol Coll Comp Changsha 410073 Hunan Peoples R China
there are only three real "dimensions" to processor performance increases beyond Moore's law: clock frequency, superscalar instruction issue, and multiprocessing. the first two have been pushed to their ... 详细信息
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TPL extension of Sande-Tucky FFT  5
TPL extension of Sande-Tucky FFT
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5th international conference on algorithms and architectures for parallel processing
作者: Huang, H Chinese Acad Sci Supercomp Ctr Comp Network Informat Ctr Beijing 100080 Peoples R China
In this paper, we use a new language-TPL (Tensor product Language) to compute the Fast Fourier Transform. It can provide good performance and portability. We detail the method and application to the FFT of TPL, andext... 详细信息
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