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Implementing Arbitrary/Common Concurrent Writes of CRCW PRAM 21

Implementing Arbitrary/Common Concurrent Writes of CRCW PRAM

引用

50th international conference on parallel processing (ICPP)

作者： Ghanim, Fady Elwasif, Wael R. Bernholdt, David E. Oak Ridge Natl Lab Oak Ridge TN 37830 USA

ISBN: (纸本)9781450384414

the parallel Random Access Machines (PRAM) abstraction is the simplest and most elegant algorithmic model for the design and analysis of parallel algorithms. It consists of different models categorized based on the underlying memory access mode used, the most powerful of which is the Concurrent Read Concurrent Write (CRCW) model. A PRAM algorithm describes a series of rounds, each of which consists of a collection of operations that can be executed concurrently within the same time step. However, the lack of support for concurrent memory accesses and the prevalence of asynchronous programming models led to the belief that implementing CRCW PRAM algorithms is unattainable and prompted many to avoid this model except for theoretical studies of optimal performance. In this work, we study the arbitrary and common concurrent writes in the CRCW PRAM model and explore implementation challenges on general-purpose systems. Moreover, we examine current practices for implementing common/arbitrary concurrent writes and propose a new efficient lightweight and thread-safe method to implement concurrent writes through leveraging atomic instructions. To demonstrate the efficacy of our method, we developed OpenMP kernels for classical CRCW PRAM algorithms and provide experimental results and comparisons based on run time performance measured over the x86 multicore architecture. Our results show a performance speedup compared to current practices up to 4.5x across all our benchmarks.

关键词： CRCW PRAM parallel algorithms Arbitrary Concurrent Writes Write-conflict resolution parallel architectures

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Bimodal Feature Propagation and Fusion for Real-time Semantic Segmentation on RGB-D Images 7

Bimodal Feature Propagation and Fusion for Real-time Semanti...

引用

7th international conference on Intelligent Computing and Signal processing, ICSP 2022

作者： He, Ying Xiao, Li Sun, Zhigang Wang, Zhuo Huazhong University of Science and Technology Key Laboratory of Image Processing and Intelligent Control Ministry of Education School of Artificial Intelligence and Automation Wuhan China

ISBN: (纸本)9781665478571

Semantic Segmentation is the foundation of scene understanding and automatic driving tasks. One of the challenges of semantic segmentation is the reduction of feature resolution as the network goes deep. In this paper, the low-resolution features are integrated into high-resolution features progressively, enabling high-resolution prediction. Currently, incorporating the auxiliary depth information into a semantic segmentation framework has proven to be helpful to improve accuracy. However, additional process of depth data immensely increases computational complexity, resulting in limitation for practical application. Here, a real-time bimodal semantic segmentation network that effectively extracts and fuses complementary information is investigated. Our network extends a light-weight architecture which can seamlessly take advantage of various prevalent backbone networks. Our model extracts RGB and depth features from two branches in parallel and integrates multi-level features of two modalities through bimodal feature fusion blocks. To reduce computation complexity, we employ depth-wise separable convolution while keep performance intact. Meanwhile, an attention mechanism is exploited to recalibrate the fusion modality features adaptively. Refinement components are retained to refine multi-resolution feature maps. We conduct ablative study to demonstrate the availability of our bimodal fusion blocks. Comprehensive experiments validate that the proposed network outperforms the state-of-the-arts and achieves 18 FPS on the challenging RGB-D dataset, NYUDv2. © 2022 IEEE.

关键词： Semantic Segmentation

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A Fast Image Matching Approach in Fatigue Testing of Wall Plate Structures

A Fast Image Matching Approach in Fatigue Testing of Wall Pl...

引用

IEEE international conference on Information Communication and Signal processing (ICICSP)

作者： Zhang Wendong Shi Baoquan Chen Xianmin Lv Yuanbo National Key Laboratory of Strength and Structural Integrity AVIC Aircraft Strength Research Institute Xi'an China School of Mechano-Electronic Engineering Xidian University Xi'an China

ISBN: (数字)9798350355895

ISBN: (纸本)9798350355901

To address the challenges in motion vector estimation due to local non-uniform deformation of specimens during fatigue tests, this paper proposes an image matching method that combines template sub-image techniques with a Kalman filter. this method employs a mesh motion estimation model, initially using the Kalman filter to predict the matching point positions of mesh nodes. Subsequently, template matching is utilized to achieve precise matching of these nodes. the algorithm is accelerated through GPU-CPU heterogeneous parallel computing technology. Test results indicate that the GPU-accelerated image matching method attains the accuracy of the CPU-based algorithm while significantly reducing processing time, thereby fully meeting the real-time requirements of online image feature matching applications.

关键词： Accuracy Deformation Image matching Signal processing algorithms Fatigue Prediction algorithms Vectors Real-time systems Kalman filters Testing

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AdaptiveBufferedthreadPool: An Rejection-Resistant Buffered thread Pool for Efficient I/O Task Handling

AdaptiveBufferedThreadPool: An Rejection-Resistant Buffered ...

引用

Software Engineering and Computer Science (CSECS), international conference on

作者： QunXiang Mao YunHui Li School Of Computer Science and Information Security Guilin University Of Electronic Technology Guilin China

ISBN: (数字)9798331522216

ISBN: (纸本)9798331522223

Existing thread pools struggle with I/O-intensive tasks: the JDK pool underutilizes CPUs due to blocking, while Tomcat wastes resources via excessive thread creation. Both frequently trigger rejection policies under high loads, risking system stability. this paper presents AdaptiveBufferedthreadPool, featuring (1) Buffer-first Rapid thread Expansion Strategy allows users to suppress excessive thread creation based on business requirements. and (2) Load-Driven Forced Queueing Model to minimize rejections. Experiments demonstrate that compared with Tomcat pool and JDK pool, AdaptiveBufferedthreadPool has higher flexibility in expanding the number of threads to curb over-creation and can achieve a task success rate of over 95% under peak load.

关键词： Instruction sets Web and internet services Pipelines Microservice architectures parallel processing Stability analysis Real-time systems thermal stability Business Software engineering

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Evolution of Configuration Data in CGP Format Using parallel GA on Embryonic Fabric 13th

Evolution of Configuration Data in CGP Format Using Parall...

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13th international conference on Innovations in Bio-Inspired Computing and Applications, IBICA 2022, and 12th World Congress on Information and Communication Technologies, WICT 2022

作者： Malhotra, Gayatri Duraiswamy, Punithavathi Kishore, J.K. U R Rao Satellite Centre Bangalore India M S Ramaiah University of Applied Sciences Bangalore India

ISBN: (纸本)9783031274985

Digital circuit configuration data can be optimized in the design space using genetic algorithms (GA). Further development of Cartesian Genetic Programming (CGP) has been made to better express data on circuit configuration. In order to realize digital circuits with the potential for self-repair with the least amount of resources, the embryonic fabric architecture has recently arisen. In this study, PHsClone (parallel Half-Sibling and Clone) GA is designed and implemented for evolving configuration data in CGP format for digital circuits built on embryonic fabric architecture. Configuration data or prospective circuit solutions can be generated more quickly using parallel processing on an FPGA. the Xilinx Virtex-7 is used to implement the planned PHsClone GA architecture. the PHsClone technique was validated using well-known benchmark circuits, including a safe mode detection circuit used in flight avionics, a 1-bit adder, a 2-bit comparator for creating 4-bit adder and 8-bit comparator circuits. According to the simulation results, four concurrent PHsClone GA executions (four parallel threads) achieve convergence for the safe mode detection circuit 37 times quicker than a single HsClone GA, 10 times faster for a 1-bit adder, and 3 times faster for a 2-bit comparator. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Genetic algorithms

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parallel Decoding of Trellis Stages for Low Latency Decoding of Tail-Biting Convolutional Codes

Parallel Decoding of Trellis Stages for Low Latency Decoding...

引用

international ITG conference on Source and Channel Coding (SCC)

作者： Amaael Antonini Wenhui Sui Zihan Qu Richard D. Wesel Department of Electrical and Computer Engineering University of California Los Angeles CA USA

ISBN: (数字)9798331522896

ISBN: (纸本)9798331522902

Convolutional codes are widely used in many applications. the encoders can be implemented with a simple circuit. Decoding is often accomplished by the Viterbi algorithm or the maximum a-posteriori decoder of Bahl et al. these algorithms are sequential in nature, requiring a decoding time proportional to the message length. For low latency applications this this latency might be problematic. this paper introduces a low latency decoder for tail-biting convolutional codes TBCCs that processes multiple trellis stages in parallel. the new decoder is designed for hardware with parallel processing capabilities. the overall decoding latency is proportional to the log of the message length. the new decoding architecture is modified into a list decoder, and the list decoding performance can be enhanced by exploiting linearity to expand the search space. Certain modifications to standard TBCCs are supported by the new architecture and improve frame error rate performance.

关键词： Convolutional codes Maximum a posteriori estimation Viterbi algorithm parallel processing Turbo codes Hardware parallel architectures Low latency communication Standards Maximum likelihood decoding

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GPU Code Generation of Cardiac Electrophysiology Simulation with MLIR 29th

GPU Code Generation of Cardiac Electrophysiology Simulation ...

引用

29th international conference on parallel and Distributed Computing (Euro-Par)

作者： Jost, Tiago Trevisan thangamani, Arun Colin, Raphael Loechner, Vincent Genaud, Stephane Bramas, Berenger Univ Strasbourg Inria Nancy Grand Est Strasbourg France Univ Strasbourg ICube Lab Strasbourg France

ISBN: (纸本)9783031396977;9783031396984

We show the benefits of the novel MLIR compiler technology to the generation of code from a DSL, namely EasyML used in openCARP, a widely used simulator in the cardiac electrophysiology community. Building on an existing work that deeply modified openCARP's native DSL code generator to enable efficient vectorized CPU code, we extend the code generation for GPUs (Nvidia CUDA and AMD ROCm). Generating optimized code for different accelerators requires specific optimizations and we review how MLIR has been used to enable multi-target code generation from an integrated generator. Experiments conducted on the 48 ionic models provided by openCARP show that the GPU code executes 3.17x faster and delivers more than 7x FLOPS per watt than the vectorized CPU code, on an Nvidia A100 GPU versus a 36-cores AVX-512 Intel CPU.

关键词： automatic GPU code generation code transformation MLIR domain-specific languages heterogeneous architectures

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Phase-Only Pattern Synthesis Using Improved Bat Algorithm

Phase-Only Pattern Synthesis Using Improved Bat Algorithm

引用

IEEE international conference on Information Communication and Signal processing (ICICSP)

作者： Ran Yang Yue Zhang Rui Guo School of Electronics and Communication Engineering Sun Yat-sen University Shenzhen China

ISBN: (数字)9798350355895

ISBN: (纸本)9798350355901

Phase-only pattern synthesis is achieved by optimizing the excitation phases of the antenna units to change the shape of the antenna pattern based on the saturation of the excitation amplitudes, which has high practical value in engineering applications. this article proposes an optimization method for phase-only symmetric pattern synthesis of phased array. Firstly, an initial phase distribution is created by a parabolic function, which has the characteristic of approximating a flat-top pattern. then, the Chebyshev polynomials are u sed to reduce the number of variables and to accelerate the optimization process. To solve this nonconvex optimization problem, the bat algorithm incorporating velocity updating weight and chaotic mapping is used. the performance of the proposed method is verified through simulation experiments.

关键词： Phased arrays Hands Fluctuations Array signal processing Shape Design methodology Signal processing algorithms Optimization methods parallel processing Polynomials

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A parallel processing System for Camera Data Checking on a Multi-Core CPU

A Parallel Processing System for Camera Data Checking on a M...

引用

IEEE international conference on Computer and Communication Engineering Technology (CCET)

作者： Hongmin Wang Yun Xu Linpeng Li Zhikai Wang Xingjian Li Liguo Song Pu Huang Ziwei Zhou Gaojin Wen Remote Sensing Laboratory Beijing Institute of Space Mechanics and Electricity Beijing P.R. China Laboratory of Computational Physics) Institute of Applied Physics and Computational Mathematics) Beijing P.R. China Laboratory of Optical Remote Sense Beijing Institute of Space Mechanics and Electricity Beijing P.R. China

ISBN: (数字)9798350355673

ISBN: (纸本)9798350355680

this paper introduces a parallel data checking system for image capture device. the system adopts a very efficient multi-threading processing software system architecture, which includes main control unit, user interface, data input/out, single frame data checking and multi-frame data checking components. Single frame data checking unit is composed of a thread scheduling unit and a thread pool. A thread scheduling algorithm is designed and implemented, which ensures that each core of the multi-core CPU can efficiently participate in data checking tasks. the efficiency and usefulness of the parallel processing system are verified by multiple image data checking tasks for space based camera.

关键词： Scheduling algorithms Multicore processing Instruction sets Process control Computer architecture parallel processing User interfaces Image capture Cameras Software systems

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A High-Speed FPGA Implementation of the Multidimensional Reconciliation for Continuous Variables Quantum Key Distribution

A High-Speed FPGA Implementation of the Multidimensional Rec...

引用

Communication, Image and Signal processing (CCISP), international conference on

作者： Jialu Sun Hao Cheng Zeyuan Jin Yong Chen Genlong Chen Lihong Ren Xueqin Jiang School of Information Science and Technology Donghua University Shanghai China

ISBN: (数字)9798350356656

ISBN: (纸本)9798350356663

For continuous variable quantum key distribution (CV-QKD) protocol, information reconciliation (IR) is a key step that can significantly affect the performance of CV-QKD. Because of multidimensional reconciliation suitable for low signal-to-noise ratio (SNR) and long transmission distance scenario, a parallel architecture for the multidimensional reconciliation in CV-QKD implemented on field programmable gate array (FPGA) is proposed in this paper. Using a binarized d-dimensional spherical vector c and a parallel computation of the coefficient a and rotation matrix M, the parallel architecture achieves 45.635 Mbps processing throughput at 250 MHz in the system clock, with frame error rate (FER) less than 0.001 when the SNR exceeds 0.71 dB.

关键词： Protocols Signal processing algorithms throughput Vectors Real-time systems Quantum key distribution parallel architectures Field programmable gate arrays Signal to noise ratio Pipeline processing

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