this paper presents a theoretical analysis in the sense of the Neyman-Pearson (N-P) test about the relationship between fusion rule and local decision rules in the parallel distributed detection fusion system with mul...
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this paper presents a theoretical analysis in the sense of the Neyman-Pearson (N-P) test about the relationship between fusion rule and local decision rules in the parallel distributed detection fusion system with multiple sensors. It combines the wavelet filter based on soft-threshold withthe parallel distributed detection fusion system with multiple sensors, and derives the determination of decision rules of two sub-optimal systems and globally optimal system completely. the detection performances of three systems above are computed numerically for the problem of detecting a known signal embedded in Rayleigh noise. the results obtained indicate that the presented method can enhance the radar detection performance remarkably.
Seismic modeling is an integral part of the seismic data processing for oil and gas exploration, as it provides us the seismic response for a given earth model. Grid enabled seismic wave modeling can facilitate users ...
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ISBN:
(纸本)3540240136
Seismic modeling is an integral part of the seismic data processing for oil and gas exploration, as it provides us the seismic response for a given earth model. Grid enabled seismic wave modeling can facilitate users in the area of geophysics to calculate synthetic seismograms using federated HPC resources and complex solution algorithms without knowing their complexities. the present paper is about componentization of the wave equation based seismic modeling algorithm and its implement using Imperial College e-Science Infrastructure (ICENI) Grid Middleware.
In several digital signal processingalgorithms, the computation is performed in consecutive stages consisting of parallel computational nodes. the stages are decoupled by data permutations where stride permutations a...
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In several digital signal processingalgorithms, the computation is performed in consecutive stages consisting of parallel computational nodes. the stages are decoupled by data permutations where stride permutations are common because of their regularity. parallel computation of such algorithms with reduced number of processing elements implies that several computational nodes are assigned to each element. As a drawback, permutations become more complex and require data storage. In this paper, register-based stride permutation networks are proposed for array processors where the storage requirement of the networks is relatively small, and thus, memory-based structures would be an expensive solution. the proposed networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the lower bound in the number of registers indicating area-efficiency. Furthermore, the networks are generated without heuristics, which makes them attractive for automated design procedures.
In this paper, we propose an efficient accelerating architecture for tier-1 coding in JPEG2000. the coding-passes-parallel method is introduced in our architecture to accelerate the encoding. A novel architecture name...
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ISBN:
(纸本)078038511X
In this paper, we propose an efficient accelerating architecture for tier-1 coding in JPEG2000. the coding-passes-parallel method is introduced in our architecture to accelerate the encoding. A novel architecture named the scan-window is employed to make it convenient to encode three coding passes in the parallel mode. therefore, three coding passes can be encoded using one time of bit-plane scan. the processing time can be reduced by more than 70% compared to the traditional serial coding passes processing architecture. Additionally, a pipelined architecture for an MQ coder is proposed to improve the throughout. the architecture has been implemented in SMIC 0.18 /spl mu/m CMOS technology.
We present a significant extension of the quantified equation based algorithm class of piecewise regular algorithms. the main contributions of the following paper are: the class of piecewise regular algorithms are ext...
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We present a significant extension of the quantified equation based algorithm class of piecewise regular algorithms. the main contributions of the following paper are: the class of piecewise regular algorithms are extended by allowing run-time dependent conditionals; a mixed integer linear program is given to derive optimal schedules of the novel class we call dynamic piecewise regular algorithms; and in order to achieve highest performance, we present a speculative scheduling approach. the results are applied to an illustrative example.
the multilevel architecture of virtual parallel computing system intended for interpretation of functional parallel programs is offered. It realizes consecutive performance of the low level operations, parallel perfor...
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the multilevel architecture of virtual parallel computing system intended for interpretation of functional parallel programs is offered. It realizes consecutive performance of the low level operations, parallel performance at a level of functions and it provide the dynamic compression of parallelism at presence of resource restrictions. Ways of increase of productivity of the interpreter are investigated.
In this paper, a new microprocessor design framework, called DOTTA (dynamic operation transport triggered array) is introduced. An FPGA (field programmable gate array) implementation of DOTTA is presented. the aim of ...
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In this paper, a new microprocessor design framework, called DOTTA (dynamic operation transport triggered array) is introduced. An FPGA (field programmable gate array) implementation of DOTTA is presented. the aim of this new processor framework is to eliminate bottlenecks introduced by traditional microprocessor architectures. the framework defines a task-specific microprocessor that is application customisable on the target system it is operating on; this has been achieved by using Xilinxtrade FPGA fabric
A carrierless UWB/OFDM system with pulse-based modulations (CL-UWB/OFDM) and its corresponding signal processingalgorithms are presented in this paper. Compared withthe traditional OFDM system, the CL-UWB/OFDM appro...
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A carrierless UWB/OFDM system with pulse-based modulations (CL-UWB/OFDM) and its corresponding signal processingalgorithms are presented in this paper. Compared withthe traditional OFDM system, the CL-UWB/OFDM approach has several distinct characteristics. Firstly, the time-domain signals generated by IDFT are real rather than complex value due to the conjugate symmetry relationship of the frequency-domain signals. Secondly, a train of extremely short pulses instead of a sinusoidal carrier is employed to convey information. thirdly, the received signals are orderly sampled through multiple parallel branches by exploiting the feature that the pulse repetition period is much larger than the duration of each pulse. Finally, the signals of each branch are independent of that of the other branches. Hence, these branches resemble the multiple fading-independent antennas in classical narrow-band systems. Due to the above properties, the CL-UWB/OFDM system has not only all virtues of the traditional OFDM system, such as resistance to multipath interference and narrow-band interference, but also other advantages, for instance, excellent immunity to fading and frequency offset, simpler transceiver, and low power spectral density.
We present a method for co-partitioning affine indexed algorithms resulting in a processor array with an optimized data-reuse. through this method, a memory hierarchy with an optimized data transfer is derived which a...
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We present a method for co-partitioning affine indexed algorithms resulting in a processor array with an optimized data-reuse. through this method, a memory hierarchy with an optimized data transfer is derived which allows a significant reduction of the power consumption caused by memory accesses. Apart from former design flows which begin with a space-time transformation, we start withthe co-partitioning of the iteration space. this allows an adaption of the resulting processor array towards the constraints of the target architecture at the beginning of the design. We illustrate our method for the full search motion estimation algorithm which bears a high potential of data-reuse.
the key technology of realizing synthetic aperture radar (SAR) imaging is real-time processing of echo signal and a lot of data memory. However, it is very difficult to finish the work of SAR imaging system with singl...
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the key technology of realizing synthetic aperture radar (SAR) imaging is real-time processing of echo signal and a lot of data memory. However, it is very difficult to finish the work of SAR imaging system with single DSP chip. In order to resolve those problems, the DSP parallelprocessing system was designed, ADSP2106x is a high-speed and real-time digital signal processor that was produced by AD Company. Using the Links port of ADSP2106x, the DSP parallelprocessing structure was devised. In the meantime, SAR imaging processing structure and the performance and characteristics of ADSP2106x were introduced, besides, the advantages and disadvantages of these methods were described. DSP parallelprocessing system can satisfy the real-time requirement of the SAR imaging signal processing and has widely applied expectation in radar, communication and image processing etc fields.
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