To accelerate the execution of most DSP(Digital Signal processing) algorithms such as FFT, FIR, Vector operations, while keeping the flexibility of the chip, a reconfigurable architecture (named ReDAr) for DSP is prop...
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ISBN:
(纸本)078037889X
To accelerate the execution of most DSP(Digital Signal processing) algorithms such as FFT, FIR, Vector operations, while keeping the flexibility of the chip, a reconfigurable architecture (named ReDAr) for DSP is proposed and implemented, and finally will be applied to the Radar system of Automatic Navigation Equipment. By analyzing these algorithms, the structure of Reconfigurable processing Element (RPE), the Crossbar interconnect network, the Memory organization. the host controlling strategy, and the data sequencing scheme of the architecture are conceived. and parts of them, including the RPE, Crossbar. data sequencer, are reconfigurable. After configuration. it can be interconnected into a parallel and pipelined framework. closely matching the algorithms and like a dedicated hardware. By simulation. the performances of these algorithms mapped onto this architecture are comparative to algorithm-specific chips in market, and satisfy the requirement of the targeted application.
the CAUSAL, RESTART and RESET mode switches, previously used to enable microscopic parallelism and improve throughput, are examined in terms of the memory requirements of the JPEG2000 block coder. An Extended Pass Swi...
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ISBN:
(纸本)0780379462
the CAUSAL, RESTART and RESET mode switches, previously used to enable microscopic parallelism and improve throughput, are examined in terms of the memory requirements of the JPEG2000 block coder. An Extended Pass Switching Arithmetic Encoder (EPSAE) is introduced that aids in the reduction of memory by providing the ability to partially process code-blocks. We show how the use of these switches and the EPSAE can reduce the overall amount of memory required by the block coder by a factor of 7. this reduction is achieved without the necessity of tight synchronization between the DWT and block coder.
A fast deductive-parallel backtraced fault simulation method uses the superposition procedure, which is oriented on large digital designs. It is proposed processing of RT and gate level design representation. the data...
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ISBN:
(纸本)9665532782
A fast deductive-parallel backtraced fault simulation method uses the superposition procedure, which is oriented on large digital designs. It is proposed processing of RT and gate level design representation. the data structure and program are oriented on algorithms for realization of proposed method and integration in automatic test pattern generation systems.
Partial reconfiguration has opened the door to efficient implementation of large applications on area constrained hardware. It requires a divide and mapping technique through which large applications are divided and m...
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the current trends in computer animations, virtual reality and augmented reality applications have resulted in the problem of texture synthesis receiving considerable attention from the computer graphics and image pro...
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ISBN:
(纸本)0780381858
the current trends in computer animations, virtual reality and augmented reality applications have resulted in the problem of texture synthesis receiving considerable attention from the computer graphics and image processing research community. In this paper we revisit the well-known texture synthesis method, image quilting, first proposed by Efros and Freeman and propose improvements to its algorithms and implementation. Further, we outline its application within a multi-resolution framework, particularly suited for modern imaging applications associated with compressed image data. We provide experimental results to prove the effectiveness of the proposed modifications and variation.
this paper describes two different approaches to optimize the performance of SoC architectures in the architecture exploration phase. Both solve the problem to map and schedule a task graph on a target architecture un...
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ISBN:
(纸本)0769518680
this paper describes two different approaches to optimize the performance of SoC architectures in the architecture exploration phase. Both solve the problem to map and schedule a task graph on a target architecture under special consideration of on-chip communications. A constructive algorithm is presented that extends previous work by taking into account potential data transfers in the future. the second approach is a recursive procedure that is based on local search techniques in a specially defined neighborhood of the critical path. Simulated annealing and tabu search are used as search algorithms. Both approaches find solutions with better performance than established methodologies. the recursive technique leads to superior results than the constructive approach, however is limited to small and mid-sized problems, whereas the constructive algorithm is not limited by this issue.
In this paper we propose two associative parallelalgorithms for the edge update of a minimum spanning tree when an edge is deleted or inserted in the underlying graph. these algorithms are represented as the correspo...
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the Ray Tracing algorithm produces realistic high quality images, but it requires a long time of calculation on a single processor machine, which limits its practical use. Withthe development of distributed objects a...
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ISBN:
(纸本)0769519881
the Ray Tracing algorithm produces realistic high quality images, but it requires a long time of calculation on a single processor machine, which limits its practical use. Withthe development of distributed objects architectures, such as CORBA (Common Object Request Broker), the most promising way to improve ray traced pictures productions seems to be parallelisation which offers both increased CPU power and memory facilities. A natural way of parallelisation is to distribute pixels over the CORBA objects system. However, since we want to deal with large scenes and making our algorithm functional over any parallel architecture system, scene objects have also to be distributed among processors, so a modified parallel algorithm is necessary. We propose a new method, which distributes the scene objects among processors (CORBA objects) according to their speed frequencies, which uses the object coherency property. Our approach of exploiting the bus CORBA gives very encouraging results.
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