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Research on Apriori Improvement Algorithm Based on MapReduce

Research on Apriori Improvement Algorithm Based on MapReduce

引用

Advanced algorithms and Control Engineering (ICAACE), international conference on

作者： Shengshai Zhang Shaowei Mei Sanda University Shanghai China University of Shanghai for Science and Technology Shanghai China Faculty of Information Technology Shanghai Jianqiao University Shanghai China

ISBN: (数字)9798350361445

ISBN: (纸本)9798350361452

With the rapid development of e-commerce, how to discover useful association rules from large-scale shopping data has become a hot research topic. Apriori algorithm is a classical algorithm in the field of association rule mining, but it has the problem of low efficiency in large-scale data mining. In order to improve the execution efficiency of Apriori algorithm, this paper proposes an improved Apriori algorithm based on MapReduce by combining the distributed processing characteristics of MapReduce. the algorithm reduces the number of self-join comparisons of the algorithm by eliminating the self-join process of k-order candidate sets and instead using (k-1)-item candidate sets to join with frequent 1-item sets to generate new k-item candidate sets. Meanwhile, this paper implements the algorithm using Hadoop distributed computing framework for large-scale data experimental validation. the experimental results show that compared with the traditional Apriori algorithm, the improved MapReduce-based Apriori algorithm has higher execution efficiency and better scalability, and can be effectively applied to large-scale data mining scenarios.

关键词： Distributed processing Control engineering Scalability Distributed databases parallel processing Data mining Electronic commerce

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Design and Implementation of FIR Filter Using Different architectures: A Comparative Study

Design and Implementation of FIR Filter Using Different Arch...

引用

international conference on Signal processing and Communication (ICSC)

作者： Teena Soni Anil Kumar Manoj Kumar Panda PDPM-IIITDM Jabalpur India

ISBN: (数字)9798331511890

ISBN: (纸本)9798331511906

the article proposes a hybrid sparse particle swarm optimization algorithm (HSPSO). this paper also presents an improved low-pass FIR filter design utilizing the HSPSO algorithm. the effectiveness of the proposed algorithm is contrasted with particle swarm optimization and sparse PSO in resolving the FIR filter design problem. HSPSO offered smaller best cost and execution time values. Furthermore, the suggested approach competes with the existing approaches in the literature, providing higher stopband attenuation values and smaller passband ripple values. the proposed work implemented the designed FIR filters, employing various multiplierless techniques, including the canonical signed digit (CSD) number system, fractional CSD (FCSD), distributed arithmetic (DA), and parallel distributed arithmetic (PDA). the comparative study of all the architectures and multiplier-based structure (MULT) is performed for the FPGA and ASIC environments. the DA outperforms all the architecture in area and power. the PDA with decomposition factor 4 provides the highest throughput and also smaller area and power compared with MULT, CSD, and FCSD-based architecture.

关键词： Costs Finite impulse response filters Signal processing algorithms throughput Attenuation Passband Particle swarm optimization Field programmable gate arrays Optimization Arithmetic

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Hybrid-driven 2D DOA Estimation Based on Uniform Circular Arrays Algorithm

Hybrid-driven 2D DOA Estimation Based on Uniform Circular Ar...

引用

IEEE international conference on Information Communication and Signal processing (ICICSP)

作者： Wenxuan Wang Tingting Lyu Zixuan Hu Dept. of Electronic Engineering Ocean University of China Qingdao China

ISBN: (数字)9798350355895

ISBN: (纸本)9798350355901

this paper proposes a hybrid driven MUSIC two-dimensional direction finding algorithm (DM-MUSIC) applied to a uniform circular array (UCA) to address the problem of traditional multi signal classification direction finding algorithms overly relying on basic model assumptions, signal distortion and reduced algorithm accuracy due to multipath effects and signal attenuation in low signal-to-noise ratio, low snapshot count, and other situations. the MUSIC model structure is enhanced using neural networks to replace the sensitive parts of the traditional algorithm such as subspace construction and peak search. the method proposed in this article first performs pattern space transformation and dimension transformation on the received signal through data preprocessing, and then uses two parallel DOA networks to predict the azimuth and elevation angles respectively. Comprehensive experiments have shown that the proposed DM-MUSIC network with a low dimensional network structure has lower complexity and better direction finding performance compared to existing direction finding models, especially under extreme signal-to-noise ratio conditions where the direction finding performance is significantly improved.

关键词： Adaptation models Two-dimensional displays Neural networks Signal processing algorithms Pattern classification Distortion Attenuation Classification algorithms Multiple signal classification Signal to noise ratio

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Large Matrix Multiplication algorithms: Analysis and Comparison 23

Large Matrix Multiplication Algorithms: Analysis and Compari...

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Proceedings of the 7th international conference on algorithms, Computing and Systems

作者： Khalil Mouhah Hind Faiz Safae Bourhnane School of Science and Engineering Al Akhawayn University Morocco

ISBN: (纸本)9798400709098

In the realm of computer science and optimization, matrices are fundamental components with a significant role across diverse applications. Matrix multiplication stands as a pivotal operation, and enhancing the efficiency of serial matrix multiplication algorithms holds key importance. this project focuses on optimizing matrix multiplication on a single computing device by exploring algorithmic approaches and optimization techniques. Matrices provide structured data representation, serving purposes ranging from dataset representation, data transformation in computer graphics, image processing, physical system modeling, to mathematical equation solving. this project concentrates specifically on algorithms for matrix multiplication. the standard algorithm computes matrix entries by directly multiplying corresponding input entries, though its efficiency degrades for larger matrices due to its high time complexity. Other algorithms like Strassen's algorithm reduce multiplications or exploit parallelism for efficiency. they employ techniques like divide-and-conquer, fast matrix multiplication, and parallel processing. In this work, these algorithms are analyzed in terms of their concepts, time complexities, and advantages. Practical performance factors like matrix size, hardware architecture, memory needs, cache efficiency, and arithmetic complexity are also explored. through benchmarking and evaluation on standard platforms, insights into their strengths and weaknesses regarding speed and resource utilization are sought. the ultimate goal is to elevate the efficiency of serial matrix multiplication algorithms in computer science and optimization. By studying and implementing a spectrum of algorithms, the project contributes to optimizing computations and enhancing matrix operation performance across scientific and engineering domains.

关键词： Intel processors Multiprocessor systems parallel computing parallel matrix multiplication Performance optimization Strassen's algorithm

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Memory Network Architecture for Packet processing in Functions Virtualization 7

Memory Network Architecture for Packet Processing in Functio...

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IEEE 7th international conference on Network Softwarization (NetSoft) - Accelerating Network Softwarization in the Cognitive Age

作者： Korikawa, Tomohiro Oki, Eiji Kyoto Univ Grad Sch Informat Kyoto Japan

ISBN: (纸本)9781665405225

Packet processing tasks in network functions issue memory requests to understand the packet information, update the packet content, and search the databases, which requires high-performance memory systems. While network functions virtualization (NFV) is expected to reduce the cost of network infrastructure by replacing dedicated network equipment with commercial off-the-shelf (COTS) hardware and virtual network functions (VNFs), VNF performance suffers from the poor memory systems that lack function-dedicated memories and memory parallelism in COTS servers. While several works presented parallel memories for packet processing based on 3 dimensional (3D)-stacked dynamic random access memories (DRAMs), data transfer latency between the processors and memories are not considered. Although there are processing-in-memory (PIM) architectures that offload a part of processing in memories to reduce data transfers, the majority of processing is still in the processors, which requires data transfers for multiple packet processing tasks. this paper proposes a memory network architecture using 3D-stacked DRAMs to increase throughput and reduce accumulated latency when there are multiple packet processing tasks. Packets that enter the memory network receive packet processing at each 3D-stacked DRAM without data transfers between the processors and memories. the evaluation results show that the proposed architecture increases throughput and reduces accumulated latency for memory accesses and data transfers when there are multiple packet processing tasks, compared to the conventional architecture with 3D-stacked DRAMbased parallel memory, where every memory access requires data transfers.

关键词： Program processors Memory management Random access memory Telecommunication traffic Data transfer throughput Network function virtualization

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SR2C: A Structurally Redundant Short Reads Collapser for Optimizing DNA Data Compression 29

SR2C: A Structurally Redundant Short Reads Collapser for Opt...

引用

29th IEEE international conference on parallel and Distributed Systems, ICPADS 2023

作者： Sun, Hui Ma, Huidong Zheng, Yingfeng Xie, Haonan Wang, Xiaofei Liu, Xiaoguang Wang, Gang Nankai University College of C.S. Nankai-Orange D.T. Joint Lab Nankai-Baidu Joint Lab ICIC TMCC SysNet DISSec GTIISC Tianjin300350 China Guangxi University School of Electrical Engineering Nanning530004 China

ISBN: (纸本)9798350330717

the current redundant sequence deduplication algorithms cannot remove structural repetitive DNA short reads such as mirror, reverse, paired, and complementary palindromes in high-throughput genomics sequencing data. Moreover, these methods also cannot construct indexes to recover the original sequences, thus failing to meet the requirements of lossless compression for downstream applications. To address these problems, we propose a data structure called Cycle-Hash-Linkage (CHL) and present a CPU parallelism optimization algorithm named SR2C (Structurally Redundant Short Reads Collapser) based on CHL to improve the compression ratio of DNA sequencing data. Experimental results on actual data from the NCBI database demonstrate that SR2C achieves an average residual sequence percentage improvement of 2.556% compared to the state-of-the-art redundant sequence deduplication algorithm, Minirmd. Furthermore, SR2C cascaded optimization improves the average compression ratios of compression algorithms Pigz, PBzip2, XZ, and 7Z by 92.345%, 78.999%, 10.132%, and 7.434%, respectively. By leveraging multi-core CPU parallel computation, SR2C effectively reduces time consumption, which achieves 2-5X deduplication and recovers *** same name Linux toolkit is freely available at https://***/fahaihi/SR2C. © 2023 IEEE.

关键词： data compression DNA sequencing data compression parallel algorithm redundancy deduplication rolling-hash algorithm structurally redundant reads

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Research on Multiple Cross-Correlation DOA Estimation Methods Under Hybrid Analog-Digital architectures on Deep Learning 8th

Research on Multiple Cross-Correlation DOA Estimation Method...

引用

8th international conference on Computing, Control and Industrial Engineering, CCIE 2024

作者： Li, Linlu Zhou, Yan Guo, Yu Wang, Guodong Northwest University Xi’an710127 China

ISBN: (纸本)9789819769360

Direction of Arrival (DOA) estimation of spatial signals is crucial in array signal processing. To address the defects of uniform linear array far-field narrowband incoherent multi-target estimation algorithms, such as poor adaptability to low signal-to-noise ratios, few predefined angles, high computational complexity, and low accuracy, and to overcome the difficulty of existing deep learning methods in effectively extracting complex-valued features of data, this paper proposes a multiple cross-correlation DOA estimation method based on deep learning with a hybrid modulus structure. this method transforms DOA estimation problem into an inverse mapping problem from the signal average power to the target arrival angle, extracts the modulus of the signal average power to construct the input data of the network, and constructs a convolutional neural network combined with an attention mechanism to extract data features. the labels of the network correspond to the arrival angles of the target, thereby achieving the DOA estimation of multiple signal sources. Simulation results indicate that this method can fully extract spatial features, improve the accuracy of DOA estimation, and reduce algorithm complexity. Meanwhile, it significantly outperforms traditional algorithms in estimation accuracy under the conditions of low signal-to-noise ratios and few predefined angles. © the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.

关键词： Cross-correlation Deep Neural Network Direction of Arrival estimation Feature Extraction Hybrid analog-digital structure

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Character Recognition Using Convolutional Neural Networks Based on CUDA

Character Recognition Using Convolutional Neural Networks Ba...

引用

international Youth conference on Radio Electronics, Electrical and Power Engineering (REEPE)

作者： Set Paing Tun Applied Mathematics and Artificial Intelligence Department National Research University “MPEI” Moscow Russian Federation

ISBN: (数字)9798331531836

ISBN: (纸本)9798331531843

the article explores character recognition using convolutional neural networks (CNNs) optimized with the CUDA platform to enhance computational efficiency. It outlines the CNN architecture, methods for leveraging GPU-based parallel data processing, and presents experimental results derived from the MNIST dataset. the study highlights that implementing CUDA drastically reduces processing time while maintaining a high level of predictive accuracy. the findings emphasize the potential of GPU acceleration in handling intensive computational tasks, making it a promising approach for real-time applications in image recognition and machine learning.

关键词： Deep learning Training Energy consumption Graphics processing units parallel processing Real-time systems Energy efficiency Convolutional neural networks Character recognition Optimization

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parallelization of BitColor Algorithm via Multithreading and GPU for Graph Coloring

Parallelization of BitColor Algorithm via Multithreading and...

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international conference on Computer Science and Engineering (UBMK)

作者： Burak Kocausta Gizem Sungu Terci Alp Arslan Bayrakci Computer Engineering Department Gebze Technical University Kocaeli Türkiye Institute of Information Technologies Gebze Technical University Kocaeli Türkiye

ISBN: (数字)9798350365887

ISBN: (纸本)9798350365894

the graph coloring problem, a fundamental NP-hard challenge, has numerous applications in scheduling, register allocation, and network optimization. Traditional sequential algorithms for graph coloring are computationally expensive, particularly for large-scale graphs. In this paper, we propose the parallel BitColor Algorithm (PBitCo), an extension of the BitColor framework, designed to exploit the parallel processing capabilities of modern CPU and GPU architectures. the PBitCo algorithm utilizes bitwise operations to reduce computation time and employs parallel execution on widely accessible platforms to further enhance performance. We implemented and tested the algorithm on various graph instances, comparing its performance against conventional graph coloring methods. Our results demonstrate that PBitCo achieves significant speedups, with the GPU implementation delivering up to a 10x improvement over baseline methods.

关键词： Computer science Processor scheduling Multithreading Graphics processing units Computer architecture Registers Resource management Optimization

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Performance optimization of Histogram Equalization for digital images using modern imaging

Performance optimization of Histogram Equalization for digit...

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international conference on Computing and Networking Technology (ICCNT)

作者： G Kalyan Kumar Anita Titus R.S. Vijayashanthi M Shalini M Dinesh Department of CSE Rajalakshmi Institute of Technology Chennai Department of ECE Jeppiaar University Chennai Department of ECE S.A. Engineering College Chennai Department of CSE St. Joseph’s College of Engineering Chennai Department of VLSI Microelectronics Saveetha School of Engineering Saveetha Institute of Medical and Technical Sciences (SIMATS) Saveetha University Chennai

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

Histogram equalization is a method of contrast adjustment in image processing using the image’s histogram. However, as modern imaging systems become more complex, these traditional algorithms for histogram equalization are no longer efficient. In response to this problem, researchers have studied several strategies for improving the performance of histogram equalization in digital images. An option is to use parallel processing and multi-threading approaches to distribute the computational burden, thereby speeding up the execution of histogram equalization. Another methodology includes using machine learning algorithms to adapt histogram equalization parameters according to the input image. Furthermore, using advanced hardware architectures like Field Programmable Gate Arrays (FPGA), Graphic processing Units (GPU), or Application Specific Integrated Circuits can significantly enhance the speed and efficiency of a Histogram Equalization. the performance optimization techniques have provided encouraging results, which significantly refine image processing time and visual perception. Modern imaging systems may benefit tremendously from their use in the new age.

关键词： Histograms Machine learning algorithms Digital images Surveillance Graphics processing units parallel processing Real-time systems Optimization Field programmable gate arrays Visual perception

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