this paper presents the first main task of a new system estimation framework for codesign located before the partitioning and architectural estimation steps. the key issue of the proposed method is a dynamic estimatio...
详细信息
ISBN:
(纸本)0780365429
this paper presents the first main task of a new system estimation framework for codesign located before the partitioning and architectural estimation steps. the key issue of the proposed method is a dynamic estimation at an abstract level (without architectural target) based on a global estimation algorithm. the proposed algorithm, addresses a given function extracted from a complex application. It is based on function orientation and combines various efficient methods to quickly explore the design space and provides the next codesign steps with a small set of candidate solutions.
this paper proposes a novel implementation of the Discrete Cosine Transform (DCT) and its inverse (IDCT) for image compression based on the Weiping Li algorithm. the proposed architecture uses only seven parallel cons...
详细信息
ISBN:
(纸本)0780365429
this paper proposes a novel implementation of the Discrete Cosine Transform (DCT) and its inverse (IDCT) for image compression based on the Weiping Li algorithm. the proposed architecture uses only seven parallel constant multipliers. these multipliers are implemented using the optimized DADDA multiplier structure resulting in minimal silicon occupation area. the resulted design, has a regular structure, simple control and interconnects, and efficient implementation of the inverse transform using the same hardware. the implementation is achieved in a single XC4036exHQ304 FPGA of Xilinx from VHDL description.
DB2 Universal Database Enterprise-Extended Edition (DB2 UDB EEE) is a parallel relational database management system using a shared nothing architecture. DB2 UDB EEE uses multiple nodes connected by an inter connect a...
详细信息
the Walsh-Hadamard transforms are important in many image processing applications including compression, filtering and code design. A novel architecture for the Fast Hadamard Transform, using distributed arithmetic te...
详细信息
ISBN:
(纸本)0780365429
the Walsh-Hadamard transforms are important in many image processing applications including compression, filtering and code design. A novel architecture for the Fast Hadamard Transform, using distributed arithmetic techniques, is proposed. In the paper, the mathematical model for the algorithm proposed, the associated design using both a distributed arithmetic ROM and Accumulator structure and a sparse matrix factorisation technique are described. the design has O(2W) computation time complexity, where W is the input wordlength, requires less area when compared with existing systolic architectures and is suitable for FPGA implementations.
this paper introduces reconfigurable computing and MorphoSys, which is a reconfigurable system. It also explains the architecture of its reconfigurable hardware part. then, it presents two spreadsheet models for the o...
详细信息
ISBN:
(纸本)0780365429
this paper introduces reconfigurable computing and MorphoSys, which is a reconfigurable system. It also explains the architecture of its reconfigurable hardware part. then, it presents two spreadsheet models for the operation of this reconfigurable device. the first spreadsheet performs the modelling through formulas, while the second does it numerically. these spreadsheet models serve as design and debugging tools.
this paper describes a design methodology of novel macro-cells for next generation ASIC libraries that has a low-power consumption and high-speed operation. In order to satisfy the desired characteristics, novel archi...
详细信息
ISBN:
(纸本)0780365429
this paper describes a design methodology of novel macro-cells for next generation ASIC libraries that has a low-power consumption and high-speed operation. In order to satisfy the desired characteristics, novel architectures of adder, multiplier, and shifter are proposed. Further, automatic layout generation programs are proposed. they are designed on the basis of the standard-cell approach and they generate the layouts of the proposed macro-cells from 8-bit to 64-bit. the proposed macro-cells are designed with a novel compound logic that consists of both CMOS logic and pass-transistor logic. they are fabricated with 0.25 /spl mu/m 1-poly 5-metal CMOS process, and have desired experimental results.
Interactive media applications have moved the ability to manipulate content as it is being streamed from a desirable feature to a required attribute for video servers. However, present day video server architectures c...
详细信息
In this paper, we have designed an efficient parallel algorithm for performing 3 D image reconstruction. In our framework, we have considered 3 D image to be reconstructed from a series of 2 D images, produced using U...
详细信息
In this paper, we have designed an efficient parallel algorithm for performing 3 D image reconstruction. In our framework, we have considered 3 D image to be reconstructed from a series of 2 D images, produced using Ultrasonography, Computer Tomography, etc. the paper discusses a general parallel algorithm for 3 D image reconstruction over CRCW, CREW and EREW PRAM models. We have developed efficient implementations of this algorithm over a vector machines, a distributed system comprising of a cluster of Work Stations and various interconnection network like mesh network and reconfigurable bus network. the performance of the above algorithms are tested using simulation experiments performed for 3 D image reconstruction of the vitreous region of the eye using ophthalmic ultrasonograms. A novel approximation scheme has also been proposed for a drastic improvement in performance for specific kinds of image. Results indicate the time complexities of the algorithms are in resonance with expected theoretical values and image obtained has a uncompromising level of accuracy.
the main idea of the Assembly Technology and its application to parallelisation of the Particle-In-Cell (PIC) method is considered. the algorithms of the PIC method realisation for multicomputers are presented. Dynami...
详细信息
ISBN:
(纸本)3540658211
the main idea of the Assembly Technology and its application to parallelisation of the Particle-In-Cell (PIC) method is considered. the algorithms of the PIC method realisation for multicomputers are presented. Dynamic load balancing for the PIC method realisation is discussed. the PIC realisation withthe assembly technology is based on construction of a fragmented parallel program which is able to send its fragments for execution in underloaded processor nodes of multicomputer. Assignment of a fragment for execution on a processor element is done dynamically in the course of execution. this is the basis of the dynamic load balancing algorithm.
暂无评论