In this paper, we have designed an efficient parallel algorithm for performing 3 D image reconstruction. In our framework, we have considered 3 D image to be reconstructed from a series of 2 D images, produced using U...
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In this paper, we have designed an efficient parallel algorithm for performing 3 D image reconstruction. In our framework, we have considered 3 D image to be reconstructed from a series of 2 D images, produced using Ultrasonography, Computer Tomography, etc. the paper discusses a general parallel algorithm for 3 D image reconstruction over CRCW, CREW and EREW PRAM models. We have developed efficient implementations of this algorithm over a vector machines, a distributed system comprising of a cluster of Work Stations and various interconnection network like mesh network and reconfigurable bus network. the performance of the above algorithms are tested using simulation experiments performed for 3 D image reconstruction of the vitreous region of the eye using ophthalmic ultrasonograms. A novel approximation scheme has also been proposed for a drastic improvement in performance for specific kinds of image. Results indicate the time complexities of the algorithms are in resonance with expected theoretical values and image obtained has a uncompromising level of accuracy.
the main idea of the Assembly Technology and its application to parallelisation of the Particle-In-Cell (PIC) method is considered. the algorithms of the PIC method realisation for multicomputers are presented. Dynami...
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ISBN:
(纸本)3540658211
the main idea of the Assembly Technology and its application to parallelisation of the Particle-In-Cell (PIC) method is considered. the algorithms of the PIC method realisation for multicomputers are presented. Dynamic load balancing for the PIC method realisation is discussed. the PIC realisation withthe assembly technology is based on construction of a fragmented parallel program which is able to send its fragments for execution in underloaded processor nodes of multicomputer. Assignment of a fragment for execution on a processor element is done dynamically in the course of execution. this is the basis of the dynamic load balancing algorithm.
A first approach to the parallel implementation of an automated visual quality inspection (VQI) system for printed ceramic dishes is described. the VQI system is conceived to detect defects on the surface drawings of ...
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A first approach to the parallel implementation of an automated visual quality inspection (VQI) system for printed ceramic dishes is described. the VQI system is conceived to detect defects on the surface drawings of dishes printed automatically on industrial series production. Quality inspection must be accomplished on-line, so a parallel implementation is proposed to speedup processing. the paper briefly introduces the algorithms employed to accomplish the various steps of quality inspection, focusing on the parallel implementation of such algorithms and the digital signal processor (DSP) platform employed. the results of the experimental tests show classification abilities of the proposed algorithms, as well as performance times for the DSP-based hardware platform and parallelization efficiency of VQI algorithms.
Following in the wake of the Accelerated Strategic Computing Initiative (ASCI) of the US Department of Energy, in the forthcoming years powerful new supercomputers will be brought into the market by the manufacturers ...
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ISBN:
(数字)9783540491644
ISBN:
(纸本)3540656413
Following in the wake of the Accelerated Strategic Computing Initiative (ASCI) of the US Department of Energy, in the forthcoming years powerful new supercomputers will be brought into the market by the manufacturers participating in the high-performance computing race. Hence, the large-scale computing facilities in the key research centers and industrial plants world-wide will surpass the teraflops performance barrier, too. the parallelarchitectures will be further extended to hierarchically clustered parallel computers mainly based on commodity-chip processors and SMP nodes tying together possibly tens of thousands of processing elements. In addition, heterogeneous computing and metacomputing will determine future large-scale computing by interconnecting supercomputers of diverse architectures as giant supercomputer complexes. these developments will challenge not only system reliability, availability and serviceability to novel levels, but also interactivity of concurrent algorithms and, in particular, adaptivity, accuracy and stability of parallel numerical methods.
the crossbreeding between advanced microprocessor design and Field Programmable Gate AI-rays (FPGAs) has produced the Field Programmable Processor Array: code named FPPA. the first integrated version has been targeted...
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ISBN:
(纸本)0769500439
the crossbreeding between advanced microprocessor design and Field Programmable Gate AI-rays (FPGAs) has produced the Field Programmable Processor Array: code named FPPA. the first integrated version has been targeted for low power consumption parallelprocessing. the FPPA is composed of a 10x10 array of RISC microcontrollers offering up to 500 MIPS at 5 MHz for processors (20 MHz for communications). the very low power feature of the core processor results in a I Watt power consumption for the whole array at 5 MHz and makes it particularly interesting for portable devices that require quite complex algorithms. In addition, FPPA principle, i.e., fault-tolerant large array of cells interconnected with an asynchronous communication scheme, is applicable on alternative structures for the cell architecture.
ForkLight is an imperative, task-parallel programming language for massively parallel shared memory machines. It is based on ANSI C, follows the SPMD model of parallel program execution, provides a sequentially consis...
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this paper describes a parallel architecture for a variety of algorithms for video compression. It has been designed to meet the requirements of encoding and decoding according to the ITU-T standard H.263. the archite...
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ISBN:
(纸本)3540664432
this paper describes a parallel architecture for a variety of algorithms for video compression. It has been designed to meet the requirements of encoding and decoding according to the ITU-T standard H.263. the architecture is an implementation of the instruction systolic array (ISA) model which combines the simplicity of systolic arrays withthe flexibility of a programmable parallel computer. Although the parallel accelerator unit is implemented on no more than 9 mm(2) of silicon it suffices to meet the compression rate necessary to send a compressed video stream through a standard ISDN terminal interface.
A one pass parallel hexagonal thinning algorithm has been developed that produces skeletons of a similar quality to those produced by a rectangular grid algorithm. A program or hardware implementation of the hexagonal...
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A one pass parallel hexagonal thinning algorithm has been developed that produces skeletons of a similar quality to those produced by a rectangular grid algorithm. A program or hardware implementation of the hexagonal algorithm was found to require only 50% of the logical operations required by the rectangular algorithm.
this paper presents a high level programming environment for FPGA-based image processing. the system is based on an FPGA Coprocessor whose high level instruction set is based on the operators of Image Algebra. the pap...
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this paper presents a high level programming environment for FPGA-based image processing. the system is based on an FPGA Coprocessor whose high level instruction set is based on the operators of Image Algebra. the paper describes the user's programming interface, and outlines the approach to generating FPGA architectures dynamically for the Image Coprocessor.
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