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4th international conference on Computer Science and Informatics, JCIS 1998, 1st international Workshop on High Performance, 1st international Workshop on Computer Vision, Pattern Recognition and Image processing Volume 4

作者： Bruda, Stefan D. Akl, Selim G. Department of Computing Queen's University Kingston Ont. K7L 3N6 Canada

Data-accumulating algorithms for sorting was investigated. For the study a bound for the running time was obtained and from the result, sorting d-algorithms was characterized in terms of complexity. It was shown that, if the data arrive too fast, then a successful algorithm must have a running time upper bounded by a constant. the results also show the importance of parallelism for the theory of d-algorithms.

关键词： parallel processing systems

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parallel computation on interval graphs using PC clusters: algorithms and experiments

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4th international conference on parallel processing, Euro-Par 1998

作者： Ferreira, A. Guérin Lassous, I. Marcus, K. Rau-Chaplin, A. CNRS INRIA Projet SLOOP BP 93 06902 Sophia Antipolis France LIAFA Université Paris 7 Case 7014 2 place Jussieu F-75251 Paris Cedex 05 France Eurecom 2229 route des Cretes 06901 Sophia Antipolis cedex France Faculty of Computer Science Dalhousie University P.O. Box 1000 Halifax NS B3J 2X4 Canada

ISBN: (纸本)3540649522

the use of PC clusters interconnected by high performance local networks is one of the major current trends in parallel/distributed computing. We give coarse-grained, BSP-like, parallel algorithms to solve many problems arising in the context of interval graphs, namely connected components, maximum weighted clique, BFS and DFS trees, minimum interval covering, maximum independent set and minimum dominating set. All of the described p-processor parallel algorithms require only constant or O(log p) number of communication rounds and are efficient in practice, as demonstrated by our experimental results obtained on a Fast Ethernet based PC cluster.

关键词： parallel algorithms

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Development of LGA & LBE 2D parallel programs

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international JOURNAL OF MODERN PHYSICS C 1998年第8期9卷 1203-1220页

作者： Ujita, H Nagata, S Akiyama, M Naitoh, M Ohashi, H Nucl Power Engn Corp Adv Simulat Syst Dept Minato Ku Tokyo Japan

A lattice-gas Automata two-dimensional program was developed for analysis of single and two-phase flow behaviors, to support the development of integrated software modules for Nuclear Power Plant mechanistic simulations. the program has single-color, which includes FHP I, II, and III models, two-color (Immiscible lattice gas), and two-velocity methods including a gravity effect model. Parameter surveys have been performed for Karman vortex street, two-phase separation for understanding flow regimes, and natural circulation flow for demonstrating passive reactor safety due to the chimney structure vessel. In addition, lattice-Boltzmann Equation two-dimensional programs were also developed. For analyzing single-phase flow behavior, a lattice-Boltzmann-BGK program was developed, which has multi-block treatments. A Finite Differential lattice-Boltzmann Equation program of parallelized version was introduced to analyze boiling two-phase flow behaviors. Parameter surveys have been performed for backward facing Bow, Karman vortex street, bent piping flow with/without obstacles for piping system applications, flow in the porous media for demonstrating porous debris coolability, Couette Row, and spinodal decomposition to understand basic phase separation mechanisms. parallelization was completed by using a domain decomposition method for all of the programs. An increase in calculation speed of at least 25 times, by parallel processing on 32 processors, demonstrated high parallelization efficiency. Application fields for microscopic model simulation to hypothetical severe conditions in large plants were also discussed.

关键词： LGA ILG two-velocity model LBGK FDLBM parallelization case study

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Field programmable gate array design for an application specific signal processing algorithms

Field programmable gate array design for an application spec...

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IEEE international Caracas conference on Devices, Circuits and Systems

作者： W.A. Moreno K. Poladia Center for Microelectronics Research University of South Florida Tampa FL USA

Field Programmable Gate Array (FPGA) architectures have emerged as an alternative means of implementing complex logic circuits providing rapid manufacturing turnaround time and low prototyping costs. this paper presents a new FPGA architecture suitable for the application specific signal processing algorithms and Wafer-Scale integration (WSI) Technology. the architecture must be designed for versatility, flexibility, high speed, improved logic density, and defect tolerance. the proposed FPGA architecture consists of 2 dimensional array of programmable logic elements based on look-up table, interconnection resources, and input/output (I/O) blocks. the architectural style is similar to the one used in XILINX FPGA architecture. A key variation from the commonly used FPGA is the dual switching scheme employed in the proposed architecture. the design methodology, the design tools, and results obtained by using a Segmented Channel Routing algorithm to map on it a 16 bit parallel multiplier, are presented.

关键词： Field programmable gate arrays Programmable logic arrays Signal processing algorithms Design methodology Logic circuits Manufacturing Prototypes Costs Wafer scale integration Logic design

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A parallel-tree switch architecture for ATM networks

A parallel-tree switch architecture for ATM networks

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international conference on Computer Communications and Networks (ICCCN)

作者： M. Al-Mouhamed H. Youssef W. Hasan Dept. of Comput. Eng. King Fahd Univ. of Pet. & Miner. Dhahran Saudi Arabia Computer Engineering Department College of Computer Science and Engineering King Fahd University of Petroleum and Minerals Dhahran Saudi Arabia King Fahd University of Petroleum & Minerals Dhahran SA

ISBN: (纸本)0818690143

We present a novel ATM switch called parallel-tree Banyan switch fabric (PTBSF) that consists of parallel Banyans arranged in a tree topology. Packets enter at the topmost Banyan. Internal conflicts are eliminated by using a conflict free 3/spl times/4 switching element which distributes conflicting cells over different Banyans. thus, cell loss may occur only at the lowest Banyan. Increasing the number of Banyans leads to noticeable decrease in the cell loss rate. the switch can be engineered to provide arbitrarily high throughput and low cell loss rate without the use of input buffering nor cell pre-processing. the performance of the switch is evaluated analytically under uniform traffic load and by simulation under a variety of ATM traffic loads. Compared to other proposed architectures, the switch exhibited stable and excellent performance with respect to cell loss and switching delay for all studied conditions as required by ATM traffic sources. the advantages of PTBF are modularity, regularity, self-routing, low processing over head, high throughput and robustness under a variety of ATM traffic conditions.

关键词： Switches Asynchronous transfer mode throughput Telecommunication traffic Fabrics Network topology Performance analysis Analytical models Performance loss Delay

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Optimization algorithms for magnetics and their parallelizability

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IEEE TRANSACTIONS ON MAGNETICS 1997年第2期33卷 1966-1969页

作者： Hoole, SRH Agarwal, K Department of Engineering Harvey Mudd College Claremont CA USA Booz Allen and Hamilton Inc. San Francisco CA USA

parallelization of optimization routines is now increasingly resorted to, because of the heavy computation associated with the optimization of electromagnetic products in the process of their design. this paper evaluated the possibilities for parallelization in electromagnetic product design. the several optimization algorithms available are evaluated for their parallelizability. It is further shown that, given the present limits of technology in relation to the number of processors available on shared memory computers of parallel architecture, parallelization in electromagnetic optimization is not necessarily worth attempting at present. thus, works of this nature, area of necessity, for the future, in readiness for that day when a new generation of parallel computer is available to us.

关键词： Magnetics Design optimization Concurrent computing Finite element methods parallel processing Algorithm design and analysis Iterative algorithms Optimization methods Product design parallel architectures

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Proceedings of the 1997 4th international conference on High Performance Computing, HiPC

Proceedings of the 1997 4th International Conference on High...

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Proceedings of the 1997 4th international conference on High Performance Computing, HiPC

the proceedings contains 80 papers from the Fourth international conference on High Performance Computing. Topics discussed include: database management systems (DBMS);data migration and caching;algorithms;programming and languages;load balancing and scheduling;reconfigurable custom computing;routing;instruction level parallelism (ILP) architectures and compiler issues;parallel input/output and multithreaded systems;virtual channels;and image processing.

关键词： parallel processing systems

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Optimal automatic hardware synthesis for signal processing algorithms

Optimal automatic hardware synthesis for signal processing a...

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13th international conference on Digital Signal processing (DSP 97)

作者： Koziris, N Economakos, G Andronikos, T Papakonstantinou, G Tsanakas, P Natl Technical Univ of Athens Zografou Greece

ISBN: (纸本)0780341376

this paper presents a complete methodology for the automatic synthesis of VLSI architectures used in digital signal processing. Most signal processing algorithms have the form of an n-dimensional nested loop with unit uniform loop carried dependencies. We model such algorithms with generalized UET grids. We calculate the optimal makespan for the generalized UET grids and then we establish the minimum number of systolic cells required achieving the optimal makespan. We present a complete methodology for the hardware synthesis of the resulting architecture, based on VHDL. this methodology automatically detects all necessary computation and communication elements and produces optimal layouts. the complexity of our proposed scheduling policy is completely independent of the size of the nested loop and depends only on its dimension, thus being the most efficient (in terms of complexity) known to us. All these methods were implemented and incorporated in an integrated software package which provides the designer with a powerful parallel design environment, from high level signal processing algorithmic specifications to low-level (i.e., actual layouts) optimal implementation. the evaluation was performed using well-known algorithms from signal processing.

关键词： VLSI circuits

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Fast arithmetic architectures for public-key algorithms over galois fields gf((2n)m) 15th

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15th international conference on the theory and application of cryptographic techniques, EUROCRYPT 1997

作者： Paar, Christof Soria-Rodriguez, Pedro ECE Department Worcester Polytechnic Institute WorcesterMA01609 United States

ISBN: (纸本)3540629750

this contribution describes a new class of arithmetic architectures for Galois fields GF(2k). the main applications of the architecture are public-key systems which are based on the discrete logarithm problem for elliptic curves. the architectures use a representation of the field GF(2k) as GF((2n)m), where k = n · m. the approach explores bit parallel arithmetic in the subfield GF(2n), and serial processing for the extension field arithmetic. this mixed parallel-serial (hybrid) approach can lead to very fast implementations. the principle of these approach was initially suggested by Mastrovito. As the core module, a hybrid multiplier is introduced and several optimizations are discussed. We provide two different approaches to squaring which, in conjunction with the multiplier, yield fast exponentiation architectures. the hybrid architectures are capable of exploring the time-space tradeoff paradigm in a flexible manner. In particular, the number of clock cycles for one field multiplication, which is the atomic operation in most public-key schemes, can be reduced by a factor of n compared to all other known realizations. the acceleration is achieved at the cost of an increased computational complexity. We describe a proof-of-concept implementation of an ASIC for exponentiation in GF((2n)m), m variable. © Springer-Verlag Berlin Heidelberg 1997.

关键词： Cryptography

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Optimally synchronizing DOACROSS loops on shared memory multiprocessors

Optimally synchronizing DOACROSS loops on shared memory mult...

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Proceedings of the 1997 international conference on parallel architectures and Compilation Techniques

作者： Rajamony, Ramakrishnan Cox, Alan L. Rice Univ Houston United States

We present two algorithms to minimize the amount of synchronization added when parallelizing a loop with loop-carried dependences. In contrast to existing schemes, our algorithms add lesser synchronization, while preserving the parallelism that can be extracted from the loop. Our first algorithm uses an interval graph representation of the dependence `overlap' to find a synchronization placement in time almost linear in the number of dependences. Although this solution may be suboptimal, it is still better than that obtained using existing methods, which first eliminate redundant dependences and then synchronize the remaining ones. Determining the optimal synchronization is an NP-complete problem. Our second algorithm therefore uses integer programming to determine the optimal solution. We first use a polynomial-time algorithm to find a minimal search space that must contain the optimal solution. then, we formulate the problem of choosing the minimal synchronization from the search space as a set-cover problem, and solve it exactly using 0-1 integer programming. We show the performance impact of our algorithms by synchronizing a set of synthetic loops on an 8-processor Convex Exemplar. the greedily synchronized loops ran between 7% and 22% faster than those synchronized by the best existing algorithm. Relative to the same base, the optimally synchronized loops ran between 10% and 22% faster.

关键词： parallel processing systems

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