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A data-flow graph generation algorithm for a coarse-grained reconfigurable processor

A data-flow graph generation algorithm for a coarse-grained ...

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international conference on ASIC

作者： Chao Yang Shouyi Yin Leibo Liu Shaojun Wei Tsinghua National Laboratory for Information Science and Technology Institute of Microelectronics Tsinghua University Beijing China Tsinghua University Beijing Beijing CN

In this paper, we present a C-to-DFG generation algorithm for coarse-grained reconfigurable processor in multimedia application field. the algorithm exploits the operation parallelism available in the sequential code; maximizes parallelism by loop unrolling and scalar replacement. Loop unrolling increases the size of basic block and fully exposes the intrinsic data parallelism. Scalar replacement eliminates memory access instructions from the basic block under the prerequisite condition of keeping data dependency. For mapping kernels, the three parts of DFGs are corresponding to the three sub-components of reconfigurable unit. the experiments evaluating the degrees of parallelism on DFGs suggest 5.2x to 120.4x speedups on four kernels from common multimedia algorithms.

关键词： Hardware parallel processing Computer languages Kernel Programming profession Chaos Embedded computing High level languages Reconfigurable architectures Bridges

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parallel Distributed processing of Constrained Skyline Queries by Filtering

Parallel Distributed Processing of Constrained Skyline Queri...

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IEEE 24th international conference on Data Engineering (ICDE 2008), vol.2

作者： Bin Cui Hua Lu Quanqing Xu Lijiang Chen Yafei Dai Yongluan Zhou Department of Computer Science Peking University China Department of Computer Science University of Aalborg Denmark Distributed Information Systems Laboratory EPF Lausanne Switzerland

ISBN: (纸本)9781424418367;1424418364

Skyline queries are capable of retrieving interesting points from a large data set according to multiple criteria. Most work on skyline queries so far has assumed a centralized storage, whereas in practice relevant data are often distributed among geographically scattered sites. In this work, we tackle constrained skyline queries in large-scale distributed environments without the assumption of any overlay structures, and propose a novel algorithm named PaDSkyline (parallel Distributed Skyline query processing). PaDSkyline significantly shortens the response time by performing parallel processing over site groups produced by a partition algorithm. Within each group, it locally optimizes the query processing over distributed sites. It also drastically enhances the network transmission efficiency by performing early reduction of skyline candidates with deliberately selected multiple filtering points. Results of extensive experiments demonstrate the efficiency and robustness of our proposals.

关键词： Distributed processing Partitioning algorithms Filtration query analysis Reaction Time Distribute parallel Lines

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parallel Approach to Fuzzy Vector Quantization for Image Compression

Parallel Approach to Fuzzy Vector Quantization for Image Com...

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ACIS international conference on Software Engineering, Artificial Intelligence, Networking, and parallel/Distributed Computing (SNPD)

作者： Huynh Van Luong Yong-Min Kim Byung-Kook Kim Jong-Myon Kim Cheol-Hong Kim School of Computer Engineering and Information Technology University of Ulsan Ulsan Korea School of Electronics and Computer Engineering Chonnam National University Gwangju Korea

Fuzzy clustering based vector quantization algorithm has been widely used in the field of data compression since the use of fuzzy clustering analysis in the early stages of a vector quantization process can make this process less sensitive to initialization. However, the process of fuzzy clustering is computationally very intensive because of its complex framework for the quantitative formulation of the uncertainty involved in the training vector space. To overcome the computational burden of the process, we introduce a parallel implementation of Fuzzy Vector Quantization (FVQ) using a representative data parallel architecture which consists of 4,096 processing elements (PEs). Our parallel approach provides a computationally efficient solution with the 4,096 PEs by employing an effective vector assignment strategy for the transition from soft to crisp decisions during the clustering process. Experimental results show that our parallel approach provides 1000times greater performance and 100times higher energy efficiency than other implementations using commercial processors such as ARM families.

关键词： Vector quantization Image coding parallel architectures Concurrent computing Energy efficiency Distributed computing Clustering algorithms Algorithm design and analysis Data compression Uncertainty

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Efficient Sparse Neural Networks Using Regularized Multi Block Sparsity Pattern on a GPU

Efficient Sparse Neural Networks Using Regularized Multi Blo...

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international conference on High Performance Computing

作者： Dharma Teja Vooturi Kishore Kothapalli Center for Security Theory and Algorithmic research (CSTAR) International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781728145365

A large portion of the computation in sparse neural networks comprises of multiplying a sparse matrix with a dense matrix, denoted SDMM in this paper. the SDMM operation with an unstructured sparsity pattern cannot be efficiently processed on modern architectures such as GPUs due to irregularity in compute and memory accesses. However, efficient parallel algorithms on a GPU can be designed for SDMM when the sparsity pattern is more structured. thus, the run time performance of sparse neural networks on a GPU is dependent on the sparsity pattern present in the underlying matrix. In sparse neural networks obtained using pruning based approaches, the choice of sparsity pattern not only effects the run time, but also effects the accuracy of the task for which the neural network is trained for. Sparsity patterns which have a good run time performance on a GPU may not have a good accuracy and vice-versa. the real challenge then is to given a target architecture, identify a sparsity pattern, a storage format, and an algorithm for SDMM that leads to sparse neural networks which are efficient in both run time and accuracy. In this work, we propose a novel, structured, flexible, and generic sparsity pattern called the RMB (Regularized Multi Block) sparsity pattern, and an efficient storage format (CRMB), and a fast GPU algorithm for processing RMBMM (SDMM with the multiplicand having RMB sparsity pattern). Using the RMB sparsity pattern, we achieve better trade-offs between the accuracy, and the run time performance of sparse neural networks on a GPU when compared to commonly used sparsity patterns like unstructured, and block sparsity patterns.

关键词： Neural networks Sparse matrices Graphics processing units parallel algorithms Computer architecture Task analysis conferences

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Exploring Predictable Redundant Instruction parallelism in Fault Tolerant Microprocessors

Exploring Predictable Redundant Instruction Parallelism in F...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Hongjun Dai Chao Yan Bin Gong Zhun Yang Tianzhou Chen Dept. of Computer Science and Technology Shandong University Jinan China Dept. of Computer Science and Technology Zhejiang University Hangzhou China

ISBN: (纸本)9781479989386

Previous strategies for instruction level temporal redundancy in super-scalar out-of-order processors have up to 45% performance degradation in certain applications compared to normal execution. the reason is that the redundant workload slows down the normal execution. Solutions are proposed to avoid certain redundant execution by reusing the result of the previously executed instructions. But there are still limitations on the instruction level parallelism and the pipeline throughput. this paper proposes a novel technique to recover the performance gap between instruction level temporal redundancy and normal execution. We present micro-architectural extensions necessary for implementing the reliability prediction and integrating it with the issue logic of a dual instruction stream superscalar core, and conduct extensive evaluations to demonstrate how well it can solve the performance problem. Experiments show that in average it can gain back nearly 71.13% of the overall IPC loss caused by redundant execution.

关键词： Pipelines Fault tolerant systems Redundancy History parallel processing

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A parallel processing model for big medical image data

A parallel processing model for big medical image data

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2014 IEEE 7th Joint international Information Technology and Artificial Intelligence conference

作者： Minye Wu Yang Zhou Zhikang Du Xing Wu School of Computer Engineering and Science Shanghai University

parallel computing has gained a great influence on scientific researches and in our daily life, especially when dealing with big data. One of the preconditions of high performance on computing is the support of efficient algorithms, which should be divisible and computing simultaneously. But not all algorithms are applicable for parallel computing, sometimes it can only make use of one single processor. In order to take full advantages of cluster or Multi-core CPUs in that case, A pipeline computation model is proposed which applies on cluster to make procedures more efficient and make full use of computer resources. Especially, our model has a very good performance on medical image process. With the model, almost all the positions of the organs in CT-images of a person could be found out simultaneously and accurately in one time, which can efficiently speed up the diagnosis of doctors, rather than the serial algorithm which can only find the position of one organ in one time before. the result of our experiment shows that the performance of the former serial algorithm has been improved by 40 percent by using our method.

关键词： A parallel processing model for big medical image data image

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Heterogeneous integration of nano devices on Si CMOS platform

Heterogeneous integration of nano devices on Si CMOS platfor...

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international conference on Solid-State and Integrated Circuit Technology

作者： K.L. Wang Fei Liu R. Ostroumov Device Research Laboratory Department of Electrical Engineering and MARCO Focus Center on Functional Engineering Nano Architectonics University of California Los Angeles Los Angeles CA USA

this paper outlines the limits on traditional scaling of CMOS and beyond, as well as the possibilities of introducing novel materials, their devices and the organization of these structures. From these organized structures, new local information processing architectures beyond CMOS may be possible. In addition to achieving continuous improvement of performance following Moore's Law, another benefit of integration is to have more functions on a Si platform. thus, the potential of heterogeneous integration of self-assembly wires, dots,and molecules, with nanometer scale feature sizes on a Si CMOS platform may lead to future integrated nanosystems, incorporating many functions beyond traditional electronics. Nanostructures enable reduction of defects and they may be formed without rigid conformation to the crystalline structure of the substrates, or in other words, they are relatively free from constraint of the crystalline substrates. thus, high performance devices and circuits may be integrated in a large area. One of the major issues for continuous increase of integration level is the increase of power dissipation per unit area on chip. We examine this critical issue of integrated circuits from a fundamental point of view of power dissipation. In order to alleviate the power dissipation issue, we study locally active devices, which may be built from homogeneous to form computational systems. Systems, such as cellular automata, cellular nonlinear networks, and other similar architectures, may be explored for low power application using nanometer scale devices and their integration.

关键词： Power dissipation Crystallization Information processing CMOS process Continuous improvement Moore's Law Self-assembly Wires Nanostructures Circuits

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Design and Implementation of Reconfigurable RS Processor

Design and Implementation of Reconfigurable RS Processor

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international conference on Integrated Circuits and Microsystems (ICICM)

作者： Fangning Li Liguo Zhang Yingzhao Hui Yuanyuan Wei Shengfei Bai Jianhao Sun School of Electronic Engineering Xi’an University of Posts & Telecommunications Xi’an China

ISBN: (纸本)9781665460583

As a representative error correction code, Reed-Solomon code is widely used in the related fields of information transmission and storage for its excellent performance. Application Specific Integrated Circuit (ASIC) is a mainstream hardware implementation solution. Although it has a high energy efficiency ratio, it has poor flexibility and cannot be applied to other communication environments. It needs to be redesigned and tape-out according to the application requirements, and the cost is enormous. Given the above problems, this paper proposes a coarse-grained reconfigurable processor suitable for RS encoding and decoding technology, which can meet the requirements of Forward Error Correction (FEC) technology in different communication scenarios. the design can conFigure RS codec circuits with different codes, different code lengths and different degrees of parallelism according to the instructions, and can support dynamic configuration of the processor under the condition that the total code length is constant and the signal code length is adjustable. there are broad application prospects in terms of flexibility.

关键词： Application specific integrated circuits Reed-Solomon codes Micromechanical devices Information processing Forward error correction parallel processing Encoding

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Memory-Optimised parallel processing of Hi-C Data

Memory-Optimised Parallel Processing of Hi-C Data

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Maurizio Drocco Claudia Misale Guilherme Peretti Pezzi Fabio Tordini Marco Aldinucci Computer Science Department University of Turin Italy

this paper presents the optimisation efforts on the creation of a graph-based mapping representation of gene adjacency. the method is based on the Hi-C process, starting from Next Generation Sequencing data, and it analyses a huge amount of static data in order to produce maps for one or more genes. Straightforward parallelisation of this scheme does not yield acceptable performance on multicore architectures since the scalability is rather limited due to the memory bound nature of the problem. this work focuses on the memory optimisations that can be applied to the graph construction algorithm and its (complex) data structures to derive a cache-oblivious algorithm and eventually to improve the memory bandwidth utilisation. We used as running example not, a tool for annotation and statistic analysis of Hi-C data that creates a gene-centric neighborhood graph. the proposed approach, which is exemplified for Hi-C, addresses several common issue in the parallelisation of memory bound algorithms for multicore. Results show that the proposed approach is able to increase the parallel speedup from 7x to 22x (on a 32-core platform). Finally, the proposed C++ implementation outperforms the first R Nu Chart prototype, by which it was not possible to complete the graph generation because of strong memory-saturation problems.

关键词： Genomics Bioinformatics Optimization Resource management Biological cells Arrays Skeleton

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Towards digital optical networks

Towards digital optical networks

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international conference on Transparent Optical Networks

作者： I. Tomkos A. Tzanakaki Athens Information Technology Center Athens Greece Athens Inf. Technol. Center Greece

ISBN: (纸本)0780392361

Technical breakthroughs in optical communications research are expected to further accelerate the realization of transparent optical networks to offer increased transmission bandwidth, integrated transmission and switching capabilities and optical signal processing functionality. this progress provides scalable, transparent and flexible end-to-end solutions in the metropolitan and access networks. these advanced optical network infrastructures will enable accessibility of new services and applications to the end user offering full access to the global information network with improved system performance and reduced cost. the primary objective of the EU COST 291 action "Towards Digital Optical Networks" is to focus on novel network concepts and architectures exploiting the features and properties of photonic technologies, to enable future telecommunications networks. It is aiming to propose a new generation of optical systems and networks that will accommodate the unpredictable and growing size of traffic demands over global distances requiring an agile communication grid supporting quality of services. this advanced photonic infrastructure will employ dense wavelength division multiplexing technologies for signal transmission and routing, optical signal processing and dynamic impairment management to eliminate the limitations of the analogue nature of traditional optical networks, and optical packet and/or burst switching to provide fine bandwidth granularity, network efficiency and flexibility. the presentation will outline resent research advancements towards the realization of digital optical networks and will present some key activities undertaken within the framework of COST 291 project.

关键词： Optical fiber networks Optical signal processing Costs Bandwidth Photonics Optical fiber communication Acceleration Communication switching System performance Mesh generation

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