We Have continued our study of a parallel perturbative learning method [Alspector et al., 1993] and implications for its implementation in analog VLSI. Our new results indicate that, in most cases, a single parallel p...
An ASIC has been designed to perform functions including digital quadrature demodulation and signal detection on an intermediate frequency signal sampled at 400 MHz in electronic warfare receivers. this performance is...
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An ASIC has been designed to perform functions including digital quadrature demodulation and signal detection on an intermediate frequency signal sampled at 400 MHz in electronic warfare receivers. this performance is achieved through a fully pipelined, parallel architecture implemented on a GaAs gate array. the hardware complexity is minimized by careful cost-performance tradeoffs in the design of the algorithms.
Scalable parallel computer architectures provide the computational performance demanded by advanced biological computing problems. NIH has developed a number of parallelalgorithms and techniques useful in determining...
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Scalable parallel computer architectures provide the computational performance demanded by advanced biological computing problems. NIH has developed a number of parallelalgorithms and techniques useful in determining biological structure and function. these applications include processing electron micrographs to determine the three-dimensional structure of viruses, calculating the solvent accessible surface area of proteins to predict the three-dimensional conformation of these molecules from their primary structure, and searching for homologous DNA sequences in large genetic databases. Timing results demonstrate substantial performance improvements withparallel implementations compared with conventional sequential systems.
Currently, many parallelalgorithms are defined for shared- memory architectures. the prefered machine model for designing these algorithms is the PRAM. However, this model does not take into account properties of exi...
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the proceedings contain 139 papers. the topics discussed include: visual speech recognition with stochastic networks;a charge-based CMOS parallel analog vector quantizer;a comparison of discrete-time operator models f...
the proceedings contain 139 papers. the topics discussed include: visual speech recognition with stochastic networks;a charge-based CMOS parallel analog vector quantizer;a comparison of discrete-time operator models for nonlinear system identification;a computational model of prefrontal cortex function;a connectionist technique for accelerated textual input: letting a network do the typing;a convolutional neural network hand tracker;a critical comparison of models for orientation and ocular dominance columns in the striate cortex;a growing neural gas network learns topologies;a Lagrangian formulation for optical backpropagation training in Kerr-type optical networks;a mixture model system for medical and machine diagnosis;and a model of the hippocampus combining self-organization and associative memory function.
In this paper we develop algorithms for performing total exchange (all-to-all broadcast) in an n-dimensional faulty SIMD hypercube, Qn, with up to n - 1 node faults. In an SIMD hypercube, during a communication step, ...
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ISBN:
(纸本)0818656026
In this paper we develop algorithms for performing total exchange (all-to-all broadcast) in an n-dimensional faulty SIMD hypercube, Qn, with up to n - 1 node faults. In an SIMD hypercube, during a communication step, nodes can exchanges information withtheir neighbors only across a specific dimension. We describe a sequence of algorithms which take N log N, N log n, 3N - 7, 2.5N--7 steps for this problem. By carefully analyzing these algorithms and a property of certain ordering of dimensions, we obtain an improved algorithm which takes 2N steps.
In this paper we present a new version of the standard multilayer perceptron (MLP) algorithm for the state-of-the-art in neural network VLSI implementations: the Intel Ni1000. this new version of the MLP uses a fundam...
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the efficiency of scheduling algorithms is essential in order to attain optimal performances from parallel programming systems. In this paper we use a portable parallel programming environment we have implemented, the...
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We present an analog VLSI chip for parallel analog vector quantization. the MOSIS 2.0 μm double-poly CMOS Tiny chip contains an array of 16 × 16 charge-based distance estimation cells, implementing a mean absolu...
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Most massively parallelarchitectures exhibit a large gap between hardware capacities and actual communication performance. Dynamic routing is the major cause of this loss of efficiency, because the interconnection ne...
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