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检索条件"任意字段=7th International Conference on Algorithms and Architectures for Parallel Processing"
2981 条 记 录,以下是2791-2800 订阅
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A Study of parallel Perturbative Gradient Descent  7
A Study of Parallel Perturbative Gradient Descent
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7th international conference on Neural Information processing Systems, NIPS 1994
作者: Lippe, D. Alspector, J. Bellcore MorristownNJ07960 United States
We Have continued our study of a parallel perturbative learning method [Alspector et al., 1993] and implications for its implementation in analog VLSI. Our new results indicate that, in most cases, a single parallel p...
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ASIC for wideband signal processing in electronic warfare systems
ASIC for wideband signal processing in electronic warfare sy...
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Proceedings of the 7th IEEE international ASIC conference and Exhibit
作者: Inkol, R.J. Esonu, M. Al-Khalili, D. Szwarc, V. Desormeaux, L. Defence Research Establishment Ottawa Ottawa Canada
An ASIC has been designed to perform functions including digital quadrature demodulation and signal detection on an intermediate frequency signal sampled at 400 MHz in electronic warfare receivers. this performance is... 详细信息
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Role of high performance parallel computing in biological research
Role of high performance parallel computing in biological re...
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Proceedings of the 16th Annual international conference of the IEEE Engineering in Medicine and Biology Society. Part 1 (of 2)
作者: Martino, Robert L. Johnson, Calvin A. Suh, Edward B. Trus, Benes L. Yap, Tieng K. Natl Inst of Health Bethesda United States
Scalable parallel computer architectures provide the computational performance demanded by advanced biological computing problems. NIH has developed a number of parallel algorithms and techniques useful in determining... 详细信息
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An approach to machine-independent parallel programming  3rd
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3rd Joint international conference on Vector and parallel processing, CONPAR 1994 - VAPP VI
作者: Zimmermann, Wolf Löwe, Welf Institut für Programm strukturen und Datenorganisation Universität Karlsruhe Karlsruhe76128 Germany
Currently, many parallel algorithms are defined for shared- memory architectures. the prefered machine model for designing these algorithms is the PRAM. However, this model does not take into account properties of exi... 详细信息
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NIPS 1994: Proceedings of the 7th international conference on Neural Information processing Systems
NIPS 1994: Proceedings of the 7th International Conference o...
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7th international conference on Neural Information processing Systems, NIPS 1994
the proceedings contain 139 papers. the topics discussed include: visual speech recognition with stochastic networks;a charge-based CMOS parallel analog vector quantizer;a comparison of discrete-time operator models f...
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Total exchange in faulty SIMD hypercubes
Total exchange in faulty SIMD hypercubes
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Proceedings of the 8th international parallel processing Symposium
作者: Sengupta, Amit Raghavendra, C.S. Washington State Univ Pullman United States
In this paper we develop algorithms for performing total exchange (all-to-all broadcast) in an n-dimensional faulty SIMD hypercube, Qn, with up to n - 1 node faults. In an SIMD hypercube, during a communication step, ... 详细信息
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the Ni1000: High Speed parallel VLSI for Implementing Multilayer Perceptrons  7
The Ni1000: High Speed Parallel VLSI for Implementing Multil...
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7th international conference on Neural Information processing Systems, NIPS 1994
作者: Perrone, Michael P. Cooper, Leon N. Thomas J. Watson Research Center P.O. Box 704 Yorktown HeightsNY10598 United States Institute for Brain and Neural Systems Brown University ProvidenceRI02912 United States
In this paper we present a new version of the standard multilayer perceptron (MLP) algorithm for the state-of-the-art in neural network VLSI implementations: the Intel Ni1000. this new version of the MLP uses a fundam... 详细信息
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Scheduling algorithms performance with the pSystem parallel programming environment  6th
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6th international conference on parallel architectures and Languages Europe, PARLE 1994
作者: Lopes, Luís M. B. Silva, Fernando M. A. LIACC Universidade do Porto Rua do Campo Alegre 823 Porto4100 Portugal
the efficiency of scheduling algorithms is essential in order to attain optimal performances from parallel programming systems. In this paper we use a portable parallel programming environment we have implemented, the... 详细信息
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A Charge-Based CMOS parallel Analog Vector Quantizer  7
A Charge-Based CMOS Parallel Analog Vector Quantizer
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7th international conference on Neural Information processing Systems, NIPS 1994
作者: Cauwenberghs, Gert Pedroni, Volnei Johns Hopkins University ECE Department 3400 N. Charles St. BaltimoreMD21218-2686 United States California Institute of Technology EE Department Mail Code 128-95 PasadenaCA91125 United States
We present an analog VLSI chip for parallel analog vector quantization. the MOSIS 2.0 μm double-poly CMOS Tiny chip contains an array of 16 × 16 charge-based distance estimation cells, implementing a mean absolu... 详细信息
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Static communications in parallel scientific programs  6th
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6th international conference on parallel architectures and Languages Europe, PARLE 1994
作者: De Lahaut, Damien Gautier Germain, Cécile LRI ura 410 du CNRS Université Paris XI Orsay cedex91405 France
Most massively parallel architectures exhibit a large gap between hardware capacities and actual communication performance. Dynamic routing is the major cause of this loss of efficiency, because the interconnection ne... 详细信息
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