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New Adiabatic Error Tolerant Adder I architectures

New Adiabatic Error Tolerant Adder I Architectures

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international conference on Signal processing and Integrated Networks (SPIN)

作者： Aditya S Kumar Abhishek Wadhwa Neeta Pandey Department of Electronics and Communication Delhi Technological University Delhi India

ISBN: (数字)9781728154756

ISBN: (纸本)9781728154763

this paper proposes two architectures of 16-bit Adiabatic Error Tolerant Adder I (ETA I). the first architecture is based on adaptation of ETA I in Adiabatic domain and is termed as AETA-I. the approximate part in AETA-I uses large number of buffers and its delay dominates the computation time, thus not fully utilizing the benefits of Approximate Computing. the second architecture addresses this issue by modifying AETA-I (META-I), processing propagate and generate bits rather than actual input values. this modification reduces the number of buffers significantly (3.42 times) and culminates into reduction in pipeline depth, power and area. the proposed adders are implemented using Positive Feedback Adiabatic Logic (PEAL) and are validated using 45nm PTM HP technology parameters in Tanner T- Spice™. For a wider comparison, PEAL based 16-bit Kogge Stone Adder (KSA) is also implemented. the proposed MAETA-I architecture has a maximum power savings of 44.94% and 30.33% at 50MHz when compared with Adiabatic KSA and AETA-I respectively.

关键词： Adiabatic Adders Handheld computers Automation Europe Design methodology Communications technology

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A decision tree for queries routing in hierarchical peer-to-peer network

A decision tree for queries routing in hierarchical peer-to-...

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the international conference on Informatics and Systems (INFOS)

作者： Anis Ismail Mohamed Quafafou Gilles Nachouki Mohammad Hajjar LSIS Universitaire de Saint-Jérôme Marseilles France LINA Laboratory Nantes France Universite Libanaise Saida Lebanon

ISBN: (纸本)9781424458288;9789774033964

Since a large amount of information is added onto the internet on a daily basis, the efficiency of peer-to-peer (P2P) search has become increasingly important. However, how to quickly discover the right resource in a large-scale P2P network without generating too much network traffic and with minimum possible time remain highly challenging. In this paper, we propose a new P2P search method by applying the concept of data mining (decision tree) in order to improve search performance. We focus on routing queries to the right destination. through a super-peer-based architecture, peers having similar interests are grouped together under a super-peer (SP) connected to a Meta-Super-Peer (MSP) operating with an index (decision tree) to predict the relevant domains (super-peers) to answer a given query. Compared with a super-peer based approach, our proposal architectures show the effect of the data mining with better performance with respect to response time and precision.

关键词： Decision trees Query processing Peer to peer computing Data mining Internet Large-scale systems Telecommunication traffic Search methods Routing Proposals

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A High-Performance Hardware Architecture for Spectral Hash Algorithm

A High-Performance Hardware Architecture for Spectral Hash A...

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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Ray C.C. Cheung Çetin K. Koc John D. Villasenor City University of Hong Kong Hong Kong China Electrical Engineering Department UCLA Los Angeles CA USA Computer Science Department University of California슠Santa Barbara Santa Barbara CA USA

the spectral hash algorithm is one of the round 1 candidates for the SHA-3 family, and is based on spectral arithmetic over a finite field, involving multidimensional discrete Fourier transformations over a finite field, data dependent permutations, rubic-type rotations, and affine and nonlinear functions. the underlying mathematical structures and operations pose interesting and challenging tasks for computer architects and hardware designers to create fast, efficient, and compact ASIC and FPGA realizations. In this paper, we present an efficient hardware architecture for the full 512-bit hash computation using the spectral hash algorithm. We have created a pipelined implementation on a Xilinx Virtex-4 XC4VLX200-11 FPGA which yields 100 MHz and occupies 38,328 slices, generating a throughput of 51.2 Gbps. Our fully parallel synthesized implementation shows that the spectral hash algorithm is about 100 times faster than the fastest SHA-1 implementation, while requiring only about 13 times as many logic slices.

关键词： Hardware Galois fields Signal processing algorithms Elliptic curve cryptography Discrete Fourier transforms Arithmetic Computer architecture Field programmable gate arrays Power engineering computing NIST

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Efficient Feature Extraction for Image Analysis through Adaptive Caching in Vector Databases

Efficient Feature Extraction for Image Analysis through Adap...

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international conference on Information and Computer Technologies (ICICT)

作者： Solmaz Seyed Monir Dongfang Zhao University of Washington United States

ISBN: (数字)9798350385625

ISBN: (纸本)9798350385632

For popular machine learning (ML) models like MobileNetV3 and ResNet, the extraction and storage of image features serve as a critical step for both the training and inference stages. Unfortunately, the state-of-the-art ML systems exhibit a performance bottleneck on the extraction and storage of image features. To that end, this paper proposes a new caching subsystem that employs an in-memory vector database. the key idea is to preprocess images using MobileNetV3 and ResNet, extract features, and store them in an in-memory vector database instance, which is realized by a MySQL deployment on the RAM disk that is extended with similarity search. the implemented enhancements, including batch insertion and parallel processing using threadPoolExecutor, have yielded a notable 36.6% improvement in the execution time of MobileNetV3 image processing compared to the sequential approach. For ResNet, the execution time without caching was 15.46 seconds, and was reduced to 11.61 seconds with parallel processing, resulting in a notable improvement of 24.9%.

关键词： Training Measurement Databases Random access memory Machine learning parallel processing Feature extraction

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Road feature extraction using a 2D LMS

Road feature extraction using a 2D LMS

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international conference on Control, Automation, Robotics and Vision (ICARCV)

作者： K.R.S. Kodagoda W.S. Wijesoma A.P. Balasuriya School of Electrical and Electronic Engineering Nanyang Technological University Singapore

In most urban roads, and similar environments such as in the theme parks, campus sites, industrial estates, science parks and the like, the painted lane markings that exist may not be easily discernible by CCD cameras due to poor lighting, bad weather conditions and inadequate maintenance. An important feature of roads in such environments is the existence of pavements or curbs on either side defining the road boundaries. these curbs, which are mostly parallel to the road, can be harnessed to extract useful features of the road for implementing autonomous navigation or driver assistance systems. However, extraction of the curb or road edge feature using vision image data is a difficult task as curbs are not conspicuous in the vision image. To extract the curb from a camera image requires extensive image processing, heuristics and very favorable lighting. In our approach, road curbs are extracted speedily using range data provided by a 2D laser measurement system (LMS). Experimental results are presented to demonstrate the viability, and effectiveness, of the proposed methodology and its robustness to different obstacle, weather and lighting conditions.

关键词： Feature extraction Least squares approximation Roads Data mining Charge coupled devices Charge-coupled image sensors Navigation Cameras Image processing Velocity measurement

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Buffer Filter: A Last-Level Cache Management Policy for CPU-GPGPU Heterogeneous System

Buffer Filter: A Last-Level Cache Management Policy for CPU-...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Songyuan Li Jinglei Meng Licheng Yu Jianliang Ma Tianzhou Chen Minghui Wu College of Computer Science and Technology Zhejiang University Hangzhou Zhejiang China Zhejiang University Hangzhou Zhejiang CN Department of Computer Science and Engineering Zhejiang University City College Hangzhou Zhejiang China

ISBN: (纸本)9781479989386

there is a growing trend towards heterogeneous systems, which contain CPUs and GPGPUs in a single chip. Managing those various on-chip resources shared between CPUs and GPGPUs, however, is a big issue and the last-level cache (LLC) is one of the most critical resources due to its impact on system performance. Some well-known cache replacement policies like LRU and DRRIP, designed for a CPU, can not be so well qualified for heterogeneous systems because the LLC will be dominated by memory accesses from thousands of threads of GPGPU applications and this may lead to significant performance downgrade for a CPU. Another reason is that a GPGPU is able to tolerate memory latency when quantity of active threads in the GPGPU is sufficient, but those policies do not utilize this feature. In this paper we propose a novel shared LLC management policy for CPU-GPGPU heterogeneous systems called Buffer Filter which takes advantage of memory latency tolerance of GPGPUs. this policy has the ability to restrict streaming requests of GPGPU by adding a buffer to memory system and vacate LLC space for cache-sensitive CPU applications. Although there is some IPC loss for GPGPU but the memory latency tolerance ensures the basic performance of GPGPU's applications. the experiments show that the Buffer Filter is able to filtrate up to 50% to 75% of the total GPGPU streaming requests at the cost of little GPGPU IPC decrease and improve the hit rate of CPU applications by 2x to 7x.

关键词： Central processing Unit Instruction sets Benchmark testing Multicore processing parallel processing System performance Memory management

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Analogic cellular PDE machines

Analogic cellular PDE machines

引用

international Joint conference on Neural Networks (IJCNN)

作者： C. Rekeczky I. Szatmari P. Foldesy T. Roska Computer and Automation Research Institute Hungary Hungarian Academy of Science Budapest Hungary Jedlik Laboratories Department of Information Technology Pázmány Péter Catholic University Budapest Hungary

this paper gives an overview on analogic cellular array architectures that can also be used to approximate partial differential equations (PDEs). Cellular arrays are massively parallel computing structures composed of cells placed on a regular grid. these cells interact locally an th e array can have both local and global dynamics. the software of this architecture is an analogic algorithm that builds on analog and logical spatio-temporal instructions of the underlying hardware, that is a locally connected cellular nonlinear network (CNN). Within this framework two classes of PDEs, motivated also by image processing methodologies will be discussed: (i) reaction-diffusion (local) types and (ii) contrast modification (global) types. It will be shown that based on cellular diffusion and wave-computing formulations these classes can be approximated on existing CNN Universal Machine (CNN-UM) chips. thus, the last generation of stored program topographic array microprocessors with integrated sensing and computing could also be viewed as the first prototypes of analogic cellular PDE machines implemented on silicon.

关键词： Computer architecture Cellular neural networks Partial differential equations parallel processing Software algorithms Hardware Cellular networks Image processing Turing machines Microprocessors

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System-level performance evaluation of a H.264/AVC encoder targeting multiprocessors architectures

System-level performance evaluation of a H.264/AVC encoder t...

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international conference on Microelectronics, ICM

作者： Hajer Krichene Zrida Ahmed Chiheb Ammari Abderrazek Jemai Mohamed Abid Department of Computer Science and Mathematics University of 7th of November Tunisia Department of Electrical Engineering CES Laboratory Sfax University Tunisia INSAT Unitéde recherche en Matériaux Mesures et Applications Tinis Tunisia Laboratoire LIP2-Faculté des Sciences de Tunis Tunis Tunisia

the system-level modeling and simulation framework Sesame/Artemis aims to efficiently explore the design space of heterogeneous embedded multimedia architectures. the Sesame environment provides several methods and tools to quickly and separately build the application process network model, the target architecture model, and the mapping model of the application onto the architecture. In addition, this tool is designed to allow the refining simulation models smoothly across different abstraction levels and to include support for refining only parts of an architecture model, creating a mixed-level simulation model. In this paper, the Sesame software framework is selected to implement at the black-box architecture model level a parallel H.264/AVC video encoding application targeting multiprocessors platforms.

关键词： Automatic voltage control Application software Computer architecture Space exploration Communication system software Software performance Computational modeling Multimedia systems System-level design Encoding

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Experimental Study on Reducing the Oscillations of a Cable-Suspended parallel Robot for Video Capturing Purposes using Simulated Annealing and Path Planning

Experimental Study on Reducing the Oscillations of a Cable-S...

引用

international conference of Signal processing and Intelligent Systems (ICSPIS)

作者： Mohammad Ghanatian Mohammad Reza Hairi Yazdi Mehdi Tale Masouleh Human and Robot Interaction Laboratory School of Mechanical Engineering University of Tehran Tehran Iran School of Mechanical Engineering University of Tehran Tehran Iran Human and Robot Interaction Laboratory School of Electrical and Computer Engineering University of Tehran Tehran Iran

ISBN: (纸本)9781665409391

this paper aims to smoothen the movements of an under-constrained cable-suspended parallel robot which carries a camera for video capturing purposes, especially for video capturing of football games. this goal is achieved by means of an accurate while simple PID controller optimized by the Simulated Annealing algorithm and implemented on the joint space. Moreover, a planning strategy is considered for the joint space trajectory of the robot which guarantees the zero jerk, acceleration, and velocity at the start and the end of motions. On this regard, a septic function for each joint of the robot is considered and the corresponding boundary conditions are applied to the function to make the end-effector movements less oscillatory. this method is implemented and tested on an experimental setup while the end-effector oscillation data is recorded using an IMU sensor attached to the end-effector of the robot. Applying frequency analysis on the oscillatory data of the end-effector reveals that this simple method, on average, resulted in a 33.8% reduction in the average amplitude of the end-effector oscillations. Moreover, the maximum joint space error was decreased by 76.68% when using septic joint profile compared to the ordinary linear Cartesian trajectory planning approach. Upon applying the proposed strategy, the error of the controller has been reduced by 92.26% with respect to the previous research performed on this experimental setup. Without requiring any knowledge on the dynamic model of the robot or the natural frequencies of the end-effector or using any complex controller, this method significantly increased the smoothness and accuracy of the robot movements. the proposed method can be regarded as a definitive asset when this robot is used for video capturing purposes.

关键词： Vibrations parallel robots Trajectory planning Simulated annealing Games Aerospace electronics End effectors

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Analysis of Sound Source Localization Effect Based on Different 18 Element 2D Microphone Arrays

Analysis of Sound Source Localization Effect Based on Differ...

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IEEE international conference on Information Communication and Signal processing (ICICSP)

作者： Jiale Fu Linsen Huang Department of Vehicle Engineering School of Mechanical Engineering Chongqing Technology and Business University Chongqing China Zonsen Industrial Group Co. Ltd Chongqing China

ISBN: (数字)9798350355895

ISBN: (纸本)9798350355901

the configuration of a microphone array entails positioning a designated quantity of microphones in precise spatial arrangements to constitute a cohesive microphone ensemble. Owing to human or environmental factors, the sound signals captured by microphone arrays frequently exhibit inherent inaccuracies. this configuration significantly impacts the outcomes of sound source localization. In real-world engineering scenarios and practical applications, the formulation of an optimal microphone array structure holds paramount significance..

关键词： Location awareness Array signal processing parallel processing Microphone arrays Environmental factors

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