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A fast VLSI architecture for two-dimensional discrete wavelet transform based on lifting scheme [image compression applications]

A fast VLSI architecture for two-dimensional discrete wavele...

引用

international conference on Solid-State and Integrated Circuit Technology

作者： Chengyi Xiong Jinwen Tian Jian Liu College of Electronic Information Engineering South-Center University of Science and Technology Wuhan China Institute of Pattern Recognition & Artification Intelligence Key Laboratory of Education Ministry for Image Processing and Intelligent Control Huazhong University of Science and Technology Wuhan China

ISBN: (纸本)078038511X

this paper proposes a novel fast architecture for a 2D discrete wavelet transform by using a lifting scheme, parallel and embedded decimation techniques are employed to optimize the architecture, which is mainly composed of two horizontal filter modules and one vertical filter module, working in parallel and pipeline fashion with 100% hardware utilization. the architecture is designed to generate two outputs in one working clock cycle, with every two subbands coefficients alternately. the total time for computing J levels of decomposition for an N/spl times/N image is approximately 2N/sup 2/(1-4/sup -J/)/3 clock cycles. In comparison with the other devices reported in previous literature, the design has many advantages including lower hardware complexity and area and power efficiency. the design is also fast, regular and simple, as well as well suited for VLSI implementation.

关键词： Discrete wavelet transforms Very large scale integration Filters Computer architecture Wavelet transforms Hardware Clocks Image coding Matrix converters Pipelines

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Transforming A Linear Algebra Core to An FFT Accelerator

Transforming A Linear Algebra Core to An FFT Accelerator

引用

IEEE international conference on Application-specific Systems, architectures and Processors

作者： Ardavan Pedram John McCalpin Andreas Gerstlauer Department of Electrical and Computer Engineering Texas Advanced Computing Center The University of Texas at Austin

ISBN: (纸本)9781479904945

this paper considers the modifications required to transform a highly-efficient, specialized linear algebra core into an efficient engine for computing Fast Fourier Transforms (FFTs). We review the minimal changes required to support Radix-4 FFT computations and propose extensions to the micro-architecture of the baseline linear algebra core. Along the way, we study the critical differences between the two classes of algorithms. Special attention is paid to the configuration of the on-chip memory system to support high utilization. We examine design trade-offs between efficiency, specialization and flexibility, and their effects both on the core and memory hierarchy for a unified design as compared to dedicated accelerators for each application. the final design is a flexible architecture that can perform both classes of applications. Results show that the proposed hybrid FFT/Linear Algebra core can achieve 26.6 GFLOPS/S with a power efficiency of 40 GFLOPS/W, which is up to 100× and 40× more energy efficient than cutting-edge CPUs and GPUs, respectively.

关键词： CPUs FFT GFLOPS/S Fast Fourier transform central processing units Linear algebra core dynamic efficiency memory hierarchy

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Adaptive artificial neural network for robust estimation of parameters of asynchronous state

Adaptive artificial neural network for robust estimation of ...

引用

international conference on Environment and Electrical Engineering (EEEIC)

作者： Pawel Kostyla Tomasz Sikorski Zbigniew Waclawek Bogdan Leszkiewicz Department of Electrical Engineering Wroclaw University of Technology Wroclaw Poland Department of Regional Economy and Tourism in Jelenia Gora Wroclaw University of Economics Wroclaw Poland

In many applications, very fast methods are required for estimating of amplitudes of current signals distorted by noise. In this paper new parallel algorithms are proposed, which can be implemented by analogue adaptive circuits employing selected neural networks principles. algorithms based on the total least-squares (TLS) and the robust total least-squares (RTLS) criteria are developed and used to detection of asynchronous state of synchronous machines. the problems are formulated as optimization tasks and solved using the steepest descent continuous-time optimization algorithm. the corresponding architectures of analogue neuron-like adaptive processors are also shown. the developed networks are more robust against noise in the measured signal than other known neural network algorithms. the network based on the TLS criterion realizes the optimization process under the assumption that the signal model can also be deteriorated (frequency or sampling interval fluctuation and so forth). the TLS estimation effect is better and more reliable than the corresponding LS structure, when higher sampling frequency and a wider sampling window is applied. An asynchronous state of a synchronous machine may be identified through determining the amplitudes of particular components of stator's current provided that a constant slip value is assumed. Following a synchronism loss, this adopted value is assumed to be achieved and, for sure, exceeded. this work provides a description of artificial neural networks realising mentioned task of asynchronous state detection. Extensive computer simulations confirm the validity and performance of the proposed algorithms.

关键词： Stators Noise Robustness Estimation Synchronous machines Optimization Signal processing algorithms

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Static Cost Estimation for Data Layout Selection on GPUs

Static Cost Estimation for Data Layout Selection on GPUs

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international Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS)

作者： Yuhan Peng Max Grossman Vivek Sarkar Department of Computer Science Rice University Houston Texas

ISBN: (纸本)9781509052196

Performance modeling provides mathematical models and quantitative analysis for designing and optimizing computer systems. In high performance architectures, high-latency memory accesses often dominate execution time in many classes of applications. thus, performance modeling for memory accesses of high performance architectures has been an important research topic. In high performance computation, data layout can significantly affect the efficiency of memory access operations. In recent years, the problem of data layout selection has been well studied on various parallel CPU and some GPU architectures. GPUs have memory hierarchies different from multi-core CPUs. While data layout selection on GPUs has been inspected by several existing projects, there is still a lack of a mathematical cost model for data layout selection on GPUs. this motivates us to investigate static cost analysis methods that could better guide future data layout selection work, and perhaps even designing new SIMT *** this paper, we propose a comprehensive cost analysis for data layout selection for GPUs. We build our cost function based on the knowledge of the GPU memory hierarchy, and develop an algorithm which allows researchers to perform compile time cost estimation for a given data layout. Furthermore, we introduce a new vector based representation to represent the estimated cost, which can better estimate the cost of applications with dynamic length loops. We apply our cost analysis to selected benchmarks from past publications on data layout selection. Our experimental results show that our cost analysis can accurately predict the relative costs of different data layouts. Using the cost model presented in this paper, we are developing an automatic data layout selection tool in our ongoing work.

关键词： Layout Graphics processing units Instruction sets Data models Computational modeling Mathematical model Estimation

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Fast Spectral Clustering Based on Fusion Density Peaks

Fast Spectral Clustering Based on Fusion Density Peaks

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international conference on Big Data and Artificial Intelligence (BDAI)

作者： Yi Gao Rong Luo Wu Yang School of Computing and Artificial Intelligence Southwest Jiaotong University Chengdu China School of Mathematics Southwest Jiaotong University Chengdu China School of Information Science and Technology Southwest Jiaotong University Chengdu China

ISBN: (数字)9798350352009

ISBN: (纸本)9798350352016

In recent years, Spectral Clustering and its variants have attracted much attention due to their excellent clustering performance. these algorithms first build a graph on the data based on local similarity, then compute the spectral decomposition of the Laplacian matrix of the graph, and finally achieve clustering by performing K-Means on embeddings obtained from spectral decomposition. However, the traditional spectral clustering method is difficult to deal with large-scale datasets. the large size of data will make the spectral decomposition slow and consume a lot of computational resources. To solve these problem, this paper first proposes a clustering algorithm named FGDPSC. FGDP-SC identifies global density peak points of the data as anchors in multi-scales defined by near-field, mid-field, and farfield, characterizes the data using a bipartite graph with anchors, and performs clustering efficiently through the transfer-cut of the bipartite graph. Experiments on real-world data validate the effectiveness of the proposed algorithms, especially on largescale data, by outperforming the classical Spectral Clustering algorithm and its main variants.

关键词： Accuracy Laplace equations Data analysis Clustering methods Buildings Clustering algorithms parallel processing Big Data Bipartite graph Matrix decomposition

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A High Energy Efficiency and Low Resource Consumption FPGA Accelerator for Convolutional Neural Network

A High Energy Efficiency and Low Resource Consumption FPGA A...

引用

international conference on Computer and Communications (ICCC)

作者： Jianwei Zhang Houjia Cai Jinghu Li Liaoning Key Lab of Integrated Circuit and Biomedical Electronic System School of Biomedical Engineering Dalian University of Technology Dalian China College of Computer and Information Sciences Fujian Agriculture and Forestry University Fuzhou China

ISBN: (纸本)9781665409513

With the rapid development of convolutional neural networks (CNN), the design of hardware accelerators for CNN calculations has become a major focus of current research. However, power consumption and resource consumption are two main limits for the application of CNN hardware accelerators. In response to these problems, a FPGA-based implementation of a CNN hardware accelerator with high energy efficiency and low resource consumption is proposed. the implementation includes zero padding, convolution, batch normalization, ReLU6, and MaxPooling. the computing performance of the network is improved by using pipeline design and layer fusion. the LeNet-5 network is to test the implementation on the Xilinx Virtex VC-707 FPGA board. the experimental result shows that when inferring the MNIST test set, the energy efficiency is 843.91 times and 228.35 times that of the CPU and GPU, respectively.

关键词： Power demand Convolution Pipelines parallel processing Energy efficiency Table lookup Convolutional neural networks

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Correlation Aware Technique for SQL to NoSQL Transformation

Correlation Aware Technique for SQL to NoSQL Transformation

引用

IEEE international conference on Ubi-Media Computing

作者： Jen-Chun Hsu Ching-Hsien Hsu Shih Chang Chen Yeh Ching Chung Chung Hua University Hsinchu TW National Tsing Hua University Hsinchu Taiwan

For better efficiency of parallel and distributed computing, Apache Hadoop distributes the imported data randomly on data nodes. this mechanism provides some advantages for general data analysis. With the same concept Apache Sqoop separates each table into four parts and randomly distributes them on data nodes. However, there is still a database performance concern with this data placement mechanism. this paper proposes a Correlation Aware method on Sqoop (CA_Sqoop) to improve the data placement. By gathering related data as closer as it could be to reduce the data transformation cost on the network and improve the performance in terms of database usage. the CA_Sqoop also considers the table correlation and size for better data locality and query efficiency. Simulation results show that data locality of CA_Sqoop is two times better than that of original Apache Sqoop.

关键词： Distributed databases Correlation Cloud computing File systems Data processing Computer architecture

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Regulating Concurrency in Software Transactional Memory: An Effective Model-based Approach

Regulating Concurrency in Software Transactional Memory: An ...

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international conference on Self-Adaptive and Self-Organizing Systems (SASO)

作者： Pierangelo Di Sanzo Francesco Del Re Diego Rughetti Bruno Ciciani Francesco Quaglia DIAG Sapienza University of Rome

Software Transactional Memory (STM) is recognized as an effective programming paradigm for concurrent applications. On the other hand, a core problem to cope with in STM deals with (dynamically) regulating the degree of concurrency, in order to deliver optimal performance. We address this problem by proposing a self-regulation approach of the concurrency level, which relies on a parametric analytical performance model aimed at predicting the scalability of the STM application as a function of the actual workload profile. the regulation scheme allows achieving optimal performance during the whole lifetime of the application via dynamic change of the number of concurrent threads according to the predictions by the model. the latter is customized for a specific application/platform through regression analysis, which is based on a lightweight sampling phase. We also present a real implementation of the model-based concurrency self-regulation architecture integrated within the open source TinySTM framework, and an experimental study based on standard STM benchmark applications.

关键词： Analytical models Concurrent computing Data models Proposals parallel processing Regression analysis Simulation

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three-dimensional angiogenesis modelling on the GPU

Three-dimensional angiogenesis modelling on the GPU

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international conference on BioMedical Engineering and Informatics (BMEI)

作者： Louis Parsonson Li Bai School of Computer Science University of Nottingham United Kingdom

Angiogenesis, the formation of de novo blood vessels, has been implicated in many human diseases, including cancer, diabetes, and in recent years, neurodegenerative diseases. Study of the formation of microvasculature, therefore, has important implications in diagnosis and treatment of diseases. this paper describes how we combine a CPU-based Cellular Potts model of sprouting angiogenesis in three dimensions with medical imaging techniques and fluid dynamics equations to create an individual-based GPU accelerated angiogenesis simulation. the use of GPU, optimized for fast, highly parallel mathematical operations, provides an increase in simulation speed and balances resource requirements across hardware. Specifically, micro-CT scans of resin cast rat cerebral vasculature are segmented and imported to instantiate nascent endothelial cells in a homogeneous three-dimensional grid representing the area over which the simulation is performed. A growth factor source is added, and simulation of steady production and diffusion of the vascular endothelial growth factor (VEGF) is performed on the GPU on the NVidia Compute Unified Device Architecture (CUDA) programming platform. Motion of individual endothelial cells is then tracked over the lifetime of the simulation towards the source of growth factor.

关键词： Mathematical model Graphics processing units Computational modeling Equations Lattices Instruction sets Arrays

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Analysis of Sound Source Localization Effect Based on Different 18 Element 2D Microphone Arrays

Analysis of Sound Source Localization Effect Based on Differ...

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IEEE international conference on Information Communication and Signal processing (ICICSP)

作者： Jiale Fu Linsen Huang Department of Vehicle Engineering School of Mechanical Engineering Chongqing Technology and Business University Chongqing China Zonsen Industrial Group Co. Ltd Chongqing China

ISBN: (数字)9798350355895

ISBN: (纸本)9798350355901

the configuration of a microphone array entails positioning a designated quantity of microphones in precise spatial arrangements to constitute a cohesive microphone ensemble. Owing to human or environmental factors, the sound signals captured by microphone arrays frequently exhibit inherent inaccuracies. this configuration significantly impacts the outcomes of sound source localization. In real-world engineering scenarios and practical applications, the formulation of an optimal microphone array structure holds paramount significance..

关键词： Location awareness Array signal processing parallel processing Microphone arrays Environmental factors

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