检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,868 篇 会议
62 册 图书
45 篇 期刊文献

馆藏范围

2,974 篇 电子文献
1 种 纸本馆藏

日期分布

学科分类号

2,085 篇 工学
- 1,865 篇 计算机科学与技术...
- 968 篇 软件工程
- 351 篇 电气工程
- 271 篇 信息与通信工程
- 267 篇 电子科学与技术（可...
- 109 篇 控制科学与工程
- 75 篇 机械工程
- 63 篇 生物工程
- 50 篇 仪器科学与技术
- 48 篇 生物医学工程（可授...
- 40 篇 动力工程及工程热...
- 37 篇 光学工程
- 33 篇 建筑学
- 30 篇 材料科学与工程（可...
- 30 篇 土木工程
- 24 篇 化学工程与技术
- 24 篇 交通运输工程
- 24 篇 网络空间安全
- 23 篇 安全科学与工程
601 篇 理学
- 397 篇 数学
- 115 篇 物理学
- 68 篇 生物学
- 62 篇 系统科学
- 41 篇 化学
- 32 篇 统计学（可授理学、...
239 篇 管理学
- 160 篇 管理科学与工程(可...
- 101 篇 图书情报与档案管...
- 72 篇 工商管理
55 篇 医学
- 48 篇 临床医学
25 篇 经济学
- 25 篇 应用经济学
21 篇 法学
15 篇 文学
14 篇 农学
4 篇 军事学
3 篇 教育学
1 篇 艺术学

主题

365 篇 parallel process...
190 篇 graphics process...
170 篇 computer archite...
135 篇 parallel archite...
121 篇 graphics process...
113 篇 hardware
106 篇 parallel algorit...
103 篇 parallel process...
83 篇 computational mo...
79 篇 instruction sets
78 篇 image processing
75 篇 signal processin...
70 篇 multicore proces...
69 篇 parallel program...
68 篇 field programmab...
63 篇 concurrent compu...
63 篇 gpu
62 篇 algorithm design...
62 篇 kernel
60 篇 optimization

机构

9 篇 natl univ def te...
6 篇 hosei univ dept ...
6 篇 school of comput...
6 篇 national laborat...
5 篇 college of compu...
5 篇 univ aizu dept c...
5 篇 college of compu...
5 篇 karlsruhe instit...
5 篇 city university ...
5 篇 st francis xavie...
4 篇 queens univ belf...
4 篇 nanyang technol ...
4 篇 chinese acad sci...
4 篇 univ chinese aca...
4 篇 hainan internati...
4 篇 department of co...
4 篇 inria rennes
4 篇 sun yat-sen univ...
4 篇 institute of com...
4 篇 university of te...

作者

11 篇 jack dongarra
8 篇 roman wyrzykowsk...
8 篇 quintana-orti en...
7 篇 hannig frank
7 篇 teich juergen
7 篇 nakano koji
7 篇 konrad karczewsk...
6 篇 ito yasuaki
6 篇 liu jie
6 篇 carretero jesus
6 篇 peng shietung
6 篇 li yamin
6 篇 chu wanming
6 篇 wang gang
5 篇 dongarra jack
5 篇 wanlei zhou
5 篇 qian depei
5 篇 namyst raymond
5 篇 ewa deelman
5 篇 dolz manuel f.

语言

2,945 篇 英文
19 篇 其他
11 篇 中文
2 篇 俄文

检索条件"任意字段=7th International Conference on Algorithms and Architectures for Parallel Processing"

共 2975 条记录，以下是2811-2820 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Taming Computation Skews of Block-Oriented Iterative Scientific Applications in MapReduce Systems

Taming Computation Skews of Block-Oriented Iterative Scienti...

引用

IEEE international conference on Cloud Computing, CLOUD

作者： Xin Yang Min Li Ze Yu Xiaolin Li Scalable Software Systems Laboratory University of Florida

Nowadays, scientists are embracing big data techniques for exploring significant discoveries from large volumes of scientific data quickly. Properly partitioning workloads is essential for fully exploiting the benefit of parallelism, but is difficult for applications whose computations change iteratively. Computation skews are inevitable when executing block-oriented iterative scientific applications in MapReduce systems. this paper proposes iPart, an autonomic workload partitioning system for taming computation skews of block-oriented iterative scientific applications in MapReduce systems. iPart introduces a workload control loop into the conventional execution of MapReduce jobs. Workload estimates in terms of execution time are collected in the reduce phase and fed back to the partition phase to update partitioning plans. Computation skews are detected and addressed by adapting partitioning to computation changes iteratively. Two adaptive partitioning methods based on the binary partitioning method are presented. Experimental evaluations with two simulated applications and the synthetic and real-world data prove that iPart responds to computation changes and adapts partitioning quickly and accurately.

关键词： Computational modeling parallel processing Synchronization Binary trees Merging

来源：评论

学校读者我要写书评

暂无评论

Partitioning and mapping a fast level-set algorithm on the GPU

Partitioning and mapping a fast level-set algorithm on the G...

引用

IEEE international Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications

作者： Julián Lamas-Rodríguez Dora B. Heras Francisco Argüello Stefan Zachow Dagmar Kainmueller CITIUS University of Santiago de Compostela Spain Visualization and Data Analysis Zuse Institute Berlin (ZIB) Germany

Level-set methods are commonly used to segment regions of interest within images or volumes. these tasks usually involve a high number of operations. GPUs nowadays feature high computation and data throughput capabilities. In this work we present two GPU implementations of the level-set-based segmentation method called Fast Two Cycle. Our solutions partition the computational domain in tiles that can be processed in parallel. the original algorithm is adapted to the special features of the GPU, and performance is optimized by keeping a record of the tiles that require processing at any given time. We have tested our implementations with a set of 3D CT images of brain vessels and we show that we can obtain competitive results using commodity hardware.

关键词： Graphics processing units Tiles Instruction sets Kernel Image segmentation Proposals three-dimensional displays

来源：评论

学校读者我要写书评

暂无评论

From Scilab to multicore embedded systems: algorithms and methodologies

From Scilab to multicore embedded systems: Algorithms and me...

引用

international conference on Embedded Computer Systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： George Goulas Panayiotis Alefragis Nikolaos S. Voros Christos Valouxis Christos Gogos Nikolaos Kavvadias Grigoris Dimitroulakos Kostas Masselos Diana Goehringer Steven Derrien Daniel Ménard Olivier Sentieys Michael Huebner Timo Stripf Oliver Oey Juergen Becker Gerard Rauwerda Kim Sunesen Dimitrios Kritharidis Nikolaos Mitas Technological Educational Institute of Mesolonghi Greece Technological Educational Institute of Epirus Greece University of Peloponnese Greece Fraunhofer-Institute of Optronics System Technologies and Image Exploitation Germany Université de Rennes I INRIA Research Institute France Ruhr-University of Bochum Germany Karlsruher Institut fur Technologie Karlsruhe Baden-WÃ¼rttemberg DE Karlsruhe Institute of Technology Germany Recore Systems The Netherlands Intracom S.A. Telecom Solutions Greece

While advances in processor architecture continues to increase hardware parallelism, parallel software creation is hard. there is an increasing need for tools and methodologies to narrow the entry gap for non-experts in parallel software development as well as to streamline the work for experts. this paper presents the methodology and algorithms for the creation of parallel software written in Scilab source code for multicore embedded processors in the context of the “Architecture oriented parallelization for high performance embedded Multicore systems using scilAb” (ALMA) EU FP7 project. the ALMA parallelization approach in a nutshell attempts to manage the complexity of the task by alternating focus between very localized and holistic view program optimization strategies.

关键词： Tiles parallel processing Optimization Multicore processing Software VLIW

来源：评论

学校读者我要写书评

暂无评论

Vedic-Based Squaring Circuit Using parallel Prefix Adders

Vedic-Based Squaring Circuit Using Parallel Prefix Adders

引用

international conference on Signal processing and Integrated Networks (SPIN)

作者： Avinash Jain Somya Bansal Shamim Akhter Shaheen Khan Department of Electronics and Communication Engineering Jaypee Institute of Information Technology Noida India Department of Electronics and Communication Engineering Mewat Engineering College Haryana India

ISBN: (数字)9781728154756

ISBN: (纸本)9781728154763

this paper proposes a novel method using Vedic mathematics for calculating the square of binary numbers. An improved Vedic multiplier architecture is used in the binary squaring circuit. the circuit is further improved by using parallel prefix adder. parallel prefix adder provides the best delay performance at the expense of area overhead. In this work, the parallel prefix adders like Kogge-Stone adder, Brent-Kung adder, Sklansky adder, Ladner-Fischer adder and Han-Carlson adder are used. the circuit is designed in Verilog HDL. the circuit synthesis has been performed in Xilinx ISE 14.7. Simulation has been performed for 4-bit and 8-bit designs. Performance comparison has been performed taking into consideration several parameters measured on different FPGA families. An improved speed performance is observed in this paper when compared with the previously reported circuits.

关键词： Adders Delays Table lookup Signal processing Hardware design languages Mathematics Integrated circuit modeling

来源：评论

学校读者我要写书评

暂无评论

A parallel Co-processor Architecture for Block Cipher processing

A Parallel Co-processor Architecture for Block Cipher Proces...

引用

2007 7th international conference on ASIC Electronic Version(ASICON 2007)

作者： Xue-Rong Yu,Zi-Bin Dai,Xiao-Hui Yang Institute of Electronic Technology,Information Engineering University,Zhengzhou 450004,P.R.China

Based on analyzing the operation character of block ciphers,we set forth a solution for efficient cryptographic processing,and put forward a parallel co-processor architecture for block ciphers,which supports word and sub-word parallel processing,and its micro realization is schemed out *** design gives attention to two aspects which is flexibility and high performance,including consummate control capability,efficient operation capability,and reconfigurable cipher process ***,in synthesis,the design is fabricated on 0.18um CMOS cells through Design Compiler tool,and the performance of this co-processor is compared to other hardware/software implementation.

关键词： Block cipher,Co-processor,Data parallelism,Instruction Level parallel

来源：评论

学校读者我要写书评

暂无评论

A decision tree for queries routing in hierarchical peer-to-peer network

A decision tree for queries routing in hierarchical peer-to-...

引用

the international conference on Informatics and Systems (INFOS)

作者： Anis Ismail Mohamed Quafafou Gilles Nachouki Mohammad Hajjar LSIS Universitaire de Saint-Jérôme Marseilles France LINA Laboratory Nantes France Universite Libanaise Saida Lebanon

ISBN: (纸本)9781424458288;9789774033964

Since a large amount of information is added onto the internet on a daily basis, the efficiency of peer-to-peer (P2P) search has become increasingly important. However, how to quickly discover the right resource in a large-scale P2P network without generating too much network traffic and with minimum possible time remain highly challenging. In this paper, we propose a new P2P search method by applying the concept of data mining (decision tree) in order to improve search performance. We focus on routing queries to the right destination. through a super-peer-based architecture, peers having similar interests are grouped together under a super-peer (SP) connected to a Meta-Super-Peer (MSP) operating with an index (decision tree) to predict the relevant domains (super-peers) to answer a given query. Compared with a super-peer based approach, our proposal architectures show the effect of the data mining with better performance with respect to response time and precision.

关键词： Decision trees Query processing Peer to peer computing Data mining Internet Large-scale systems Telecommunication traffic Search methods Routing Proposals

来源：评论

学校读者我要写书评

暂无评论

Road feature extraction using a 2D LMS

Road feature extraction using a 2D LMS

引用

international conference on Control, Automation, Robotics and Vision (ICARCV)

作者： K.R.S. Kodagoda W.S. Wijesoma A.P. Balasuriya School of Electrical and Electronic Engineering Nanyang Technological University Singapore

In most urban roads, and similar environments such as in the theme parks, campus sites, industrial estates, science parks and the like, the painted lane markings that exist may not be easily discernible by CCD cameras due to poor lighting, bad weather conditions and inadequate maintenance. An important feature of roads in such environments is the existence of pavements or curbs on either side defining the road boundaries. these curbs, which are mostly parallel to the road, can be harnessed to extract useful features of the road for implementing autonomous navigation or driver assistance systems. However, extraction of the curb or road edge feature using vision image data is a difficult task as curbs are not conspicuous in the vision image. To extract the curb from a camera image requires extensive image processing, heuristics and very favorable lighting. In our approach, road curbs are extracted speedily using range data provided by a 2D laser measurement system (LMS). Experimental results are presented to demonstrate the viability, and effectiveness, of the proposed methodology and its robustness to different obstacle, weather and lighting conditions.

关键词： Feature extraction Least squares approximation Roads Data mining Charge coupled devices Charge-coupled image sensors Navigation Cameras Image processing Velocity measurement

来源：评论

学校读者我要写书评

暂无评论

Pipeline Architecture for N==K*2L Bit Modular ALU: Case Study between Current Generation Computing and Vedic Computing

Pipeline Architecture for N==K*2L Bit Modular ALU: Case Stud...

引用

international conference for Convergence of Technology (I2CT)

作者： G.N. Chiranjeevi Subhash Kulkarni Department of Electronics and Communication Engineering PESIT-Bangalore South Campus Bangalore Affiliated to Visvesvaraya Technological University Belagavi Karnataka India

ISBN: (纸本)9781728188768;9781728188775

this paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. these algorithm have been evaluated with better performance, area and speed. the literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. the proposition is on realizing N-bit using `2^L, as base modules using `K' modules in pipelining. the authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU the authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

关键词： Computational modeling Signal processing algorithms Process control Computer architecture Digital signal processing parallel architectures Delays

来源：评论

学校读者我要写书评

暂无评论

New Adiabatic Error Tolerant Adder I architectures

New Adiabatic Error Tolerant Adder I Architectures

引用

international conference on Signal processing and Integrated Networks (SPIN)

作者： Aditya S Kumar Abhishek Wadhwa Neeta Pandey Department of Electronics and Communication Delhi Technological University Delhi India

ISBN: (数字)9781728154756

ISBN: (纸本)9781728154763

this paper proposes two architectures of 16-bit Adiabatic Error Tolerant Adder I (ETA I). the first architecture is based on adaptation of ETA I in Adiabatic domain and is termed as AETA-I. the approximate part in AETA-I uses large number of buffers and its delay dominates the computation time, thus not fully utilizing the benefits of Approximate Computing. the second architecture addresses this issue by modifying AETA-I (META-I), processing propagate and generate bits rather than actual input values. this modification reduces the number of buffers significantly (3.42 times) and culminates into reduction in pipeline depth, power and area. the proposed adders are implemented using Positive Feedback Adiabatic Logic (PEAL) and are validated using 45nm PTM HP technology parameters in Tanner T- Spice™. For a wider comparison, PEAL based 16-bit Kogge Stone Adder (KSA) is also implemented. the proposed MAETA-I architecture has a maximum power savings of 44.94% and 30.33% at 50MHz when compared with Adiabatic KSA and AETA-I respectively.

关键词： Adiabatic Adders Handheld computers Automation Europe Design methodology Communications technology

来源：评论

学校读者我要写书评

暂无评论

GPU Implementation of Orthogonal Matching Pursuit for Compressive Sensing

GPU Implementation of Orthogonal Matching Pursuit for Compre...

引用

international conference on parallel and Distributed Systems (ICPADS)

作者： Yong Fang Liang Chen Jiaji Wu Bormin Huang College of Information Engineering Northwest A&F University Angling Shaanxi China College of Information Engineering Northwest A&F University Yangling Shaanxi China Key Laboratory Intelligent Perception & Image Understanding of Ministry of Education Xidian University Xi'an Shaanxi China Space Science & Engineering Center University of Wisconsin-Madison Madison USA

Recovery algorithms play a key role in compressive sampling (CS). Currently, a popular recovery algorithm for CS is the orthogonal matching pursuit (OMP), which possesses the merits of low complexity and good recovery quality. Considering that the OMP involves massive matrix/vector operations, it is very suited to being implemented in parallel on graphics processing unit (GPU). In this paper, we first analyze the complexity of each module in the OMP and point out the bottlenecks of the OMP lie in the projection module and the least-squares module. To speedup the projection module, Fujimoto's matrix-vector multiplication algorithm is adopted. To speedup the least-squares module, the matrix-inverse-update algorithm is adopted. Experimental results show that +40x speedup is achieved by our implementation of OMP on GTX480 GPU over on Intel(R) Core(TM) i7 CPU. Since the projection module occupies more than 2/3 of the total run time, we are looking for a faster matrix-vector multiplication algorithm.

关键词： Graphics processing unit Matching pursuit algorithms Complexity theory Instruction sets Vectors Kernel Registers

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共298页 << < 278 279 280 281 282 283 284 285 286 287 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：