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Analogic cellular PDE machines

Analogic cellular PDE machines

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international Joint conference on Neural Networks (IJCNN)

作者： C. Rekeczky I. Szatmari P. Foldesy T. Roska Computer and Automation Research Institute Hungary Hungarian Academy of Science Budapest Hungary Jedlik Laboratories Department of Information Technology Pázmány Péter Catholic University Budapest Hungary

this paper gives an overview on analogic cellular array architectures that can also be used to approximate partial differential equations (PDEs). Cellular arrays are massively parallel computing structures composed of cells placed on a regular grid. these cells interact locally an th e array can have both local and global dynamics. the software of this architecture is an analogic algorithm that builds on analog and logical spatio-temporal instructions of the underlying hardware, that is a locally connected cellular nonlinear network (CNN). Within this framework two classes of PDEs, motivated also by image processing methodologies will be discussed: (i) reaction-diffusion (local) types and (ii) contrast modification (global) types. It will be shown that based on cellular diffusion and wave-computing formulations these classes can be approximated on existing CNN Universal Machine (CNN-UM) chips. thus, the last generation of stored program topographic array microprocessors with integrated sensing and computing could also be viewed as the first prototypes of analogic cellular PDE machines implemented on silicon.

关键词： Computer architecture Cellular neural networks Partial differential equations parallel processing Software algorithms Hardware Cellular networks Image processing Turing machines Microprocessors

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Accelerating range-based loops on heterogeneous systems

Accelerating range-based loops on heterogeneous systems

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international conference on Knowledge and Smart Technology (KST)

作者： Chaturapat Suwancharoen Worawan Marurngsith Department of Computer Science Thammasat University Pathum Thani Thailand Thammasat University Bangkok TH

Range-based loop is a powerful construct due to its clear and concise syntax. the abstraction of loop index in a range-based loop implies loop-level parallelism ready to be exploited. Despite its advantage on hidden parallelism and programmability, the magnitude of performance gain by accelerating range-based loop on heterogeneous systems is still not well studied. this paper addresses this issue and make three contributions. First, the review showing the magnitude of performance gain from CUDA/OpenCL code, generated by ten exisiting auto-parallelizing compilers is presented. Second, the performance comparison between range-based and traditional loops acceleration on four workloads from the SHOC benchmark is reported. third, the performance limitation on using directive-based compiler to accelerate range-based loop is discussed. the results show that transforming scientific workloads to exploit range-based loops is a challenge. the review results show that code generated by auto-parallelizing achieved an average of 37±23 folds speedup relative to sequential CPU, while the proposed range-based compiler achieved higher speedup than the average (44.8±22x). the evaluation against four workloads from highly-tuned benchmark shows that range-based loop acceleration achieved in average 72% of the benchmark's performance. this highlights range-based loops as a promising target for auto parallelizing compiling code on heterogeneous systems.

关键词： Acceleration Graphics processing units Benchmark testing Performance gain Performance evaluation parallel processing Containers

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CA-Market: A Partially Categorical AnnotatingApproach Based on Market1501 Dataset for Attribute Detection

CA-Market: A Partially Categorical AnnotatingApproach Based ...

引用

international conference of Signal processing and Intelligent Systems (ICSPIS)

作者： Hossein Bodaghi Shayan Samiee Mehdi Tale Masoulehe Ahmad Kalhor Human and Robot Interaction Laboratory University of Tehran Tehran Iran

ISBN: (纸本)9781665409391

In this paper, a new partial categorical attributes dataset (CA-Market) based on images of the Market1501 dataset has been introduced, for the sake of improving the attribute detection task. Most attributes detection datasets (human appearance features detection) are not partially categorical and do not properly take into account the inner classes diversity. Increasing the diversity of inner parts (gender, head, upper-body clothes, lower-body clothes, bags, shoes, and colors) before annotating can ease the decision-making process by dividing labels into individual categories. CA-Market contains 46 binary attributes in 10 parts from head to foot and their colors which are annotated in image-level. For example, the attributes of the leg part are skirts, shorts, and pants which are carefully chosen to be categorized for a classification task. In this research, the effect of the labeling approach is studied. Hence, a common classification method is used and only datasets or baselines are changed for comparisons. Baselines are based on Omni-Scale, Resnet50, and Hydra-Plus architectures to compare the CA-Market1501 dataset with the Market1501 attribute dataset in the same setting. CA-Market demonstrates a new representation of data as a part-based format which can gain better results. this approach, without adding any extra modules, achieved a significant enhancement. For instance, accuracy in the vectorized format is over 92%, in the categorized is over 90% which shows the effectiveness of part-based attribute annotating. Also, hair, backpack, upper color, and lower color as the common attributes between Market1501-attribute and CA-Market datasets are achieved 90.26, 88.04, 94.55, and 94.18 classification accuracy which can outperform existing state-of- the-art approaches.

关键词： Hair Measurement Legged locomotion Head Image color analysis Signal processing Labeling

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A novel architecture for Walsh Hadamard transforms using distributed arithmetic principles

A novel architecture for Walsh Hadamard transforms using dis...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： A. Amira A. Bouridane P. Milligan School of Computer Science Queen''s University Belfast Belfast UK

ISBN: (纸本)0780365429

the Walsh-Hadamard transforms are important in many image processing applications including compression, filtering and code design. A novel architecture for the Fast Hadamard Transform, using distributed arithmetic techniques, is proposed. In the paper, the mathematical model for the algorithm proposed, the associated design using both a distributed arithmetic ROM and Accumulator structure and a sparse matrix factorisation technique are described. the design has O(2W) computation time complexity, where W is the input wordlength, requires less area when compared with existing systolic architectures and is suitable for FPGA implementations.

关键词： Computer architecture Arithmetic Image processing Image coding Filtering Mathematical model Algorithm design and analysis Read only memory Sparse matrices Field programmable gate arrays

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GPU parallelization and Optimization of a Combustion Simulation Application

GPU Parallelization and Optimization of a Combustion Simulat...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Zhixiang Liao Yongzhou Liu Yonggang Che State Key Laboratory of High Performance Computing Institute for Quantum Information College of Computer National University of Defense Technology Changsha China

Graphics processing units (GPUs) are widely used in the area of scientific computing. While GPUs provide much higher peak performance, efficient implementation of real applications on the GPU architectures is still a non-trivial task. It is crucial to realize efficient solution algorithms that can better utilize GPU architectures. this paper presents our efforts in parallelizing and optimizing LESAP, a CFD application for scramjet combustion simulation, on NVIDIA GPUs. the GPU parallelization is realized based on the CUDA programming model, with a data-parallel implicit time-marching method that is efficient on the GPU architecture. Furthermore, shared memory and redundant calculation are proposed to reduce memory access overhead during GPU computation, and data transfer between CPU and GPU is optimized by packing the data to be transferred. the experimental results show that the GPU version, when runs on four V100 GPUs, achieves a speedup of 11.26 times compared to the CPU version that runs on two 24-core Intel Skylake Gold 6240R CPUs. Excellent parallel scalability across multiple GPUs is also observed.

关键词： Gold Smart cities Computational modeling Graphics processing units Computer architecture Combustion Central processing Unit

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A Novel Steady and Redundant Frames Removal Performance Analysis of Video Background Subtraction algorithms with YOLOx Models

A Novel Steady and Redundant Frames Removal Performance Anal...

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Mobile Networks and Wireless Communications (ICMNWC), IEEE international conference on

作者： Sonali Karale Jatinderkumar R. Saini School of Computer Science and IT Jain (Deemed-to-be University) Bangalore India Symbiosis Institute of Computer Studies and Research Symbiosis International (Deemed University) Pune India

ISBN: (数字)9798331528348

ISBN: (纸本)9798331528355

One of the prime research areas today is video summarisation, where the short summary of the input video is generated. the output video content is based on the object of interest. It also saves the time of the viewer; they won't need to view the entire long duration video. To do this process faster, the redundant or steady frames need to be removed first. Background subtraction is one of the techniques used to identify moving objects by calculating the difference between previous and current frame. In our research paper, we have used KNN, MOG2 and CNT for the BGS methods. We have also used different YOLO model like YOLOv3, YOLOv5, YOLOv7 and YOLOv8 to generate annotations file and use them for measuring the performance of the BS algorithms. these methods are implemented using parallel processing approach to process more than one video at a time. the performance analysis of these methods is done based on the time of execution and precision. the experiment result shows that the KNN with YOLOv7 perform better and parallel processing approach speedup the execution.

关键词： YOLO Wireless communication Analytical models Instruction sets Nearest neighbor methods parallel processing Time measurement Libraries Performance analysis Object recognition

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An approximation algorithm for scheduling dependent tasks on m processors with small communication delays

An approximation algorithm for scheduling dependent tasks on...

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： C. Hanen A. Munier LITP IBP Université Pierre et Marie Curie Paris France

this paper defines and studies an approximation algorithm for scheduling tasks with small communication delays on parallel processors. In a first step, a schedule for the relaxed problem instance with an unlimited number of processors is generated. then this solution is used to solve the resource conflicts during the scheduling phase on m processors, with a rather unusual feature: a feasible task may be tactically delayed, even inducing idleness on a processor in order to wait for a more important task. the relative worst case performance of this algorithm is analysed with respect to the ratio between communication times and processing times and to the performance of the relaxed solution. It improves significantly the best known performance ratio of an algorithm for this problem (7/3 against 3).

关键词： Approximation algorithms Scheduling algorithm Processor scheduling Clustering algorithms Performance analysis Algorithm design and analysis parallel architectures Delay systems

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FPGA Implementation Of a High throughput Low Power Advanced Encryption Standard (AES-128) Cipher

FPGA Implementation Of a High Throughput Low Power Advanced ...

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international conference on Signal processing and Integrated Networks (SPIN)

作者： Jaideep Kala Jeebananda Panda Lavi Tanwar Department of Electronics and Communication Delhi Technological University New Delhi India

Ensuring secure transmission and storage of digital information is critical for any organization to function properly. To address this issue, encryption algorithms are commonly used. Advanced Encryption Standard (AES) has been globally adopted as the mainstay cipher algorithm for securing transmission networks and storage devices due to its easy implementation and compatibility with both hardware and software applications. Another reason for its widespread popularity is its uncompromisable nature against existing brute force attacks, making it practically unbreakable on existing computing power. AES implementation for battery operated devices requires an algorithm with low power consumption and high-speed encryption/decryption of digital data. this paper proposes an FPGA implementation of a high throughput parallel pipelined 128-bit AES algorithm with a low power key expansion mechanism for iterative stages. A 128-bit symmetric key has been used for undertaking 10 rounds of transformations. All the encryption and decryption transformations are simulated using iterative design methodology in order to minimize hardware consumption. Xilinx Artix-7 FPGA device is used for hardware evaluation and Verilog HDL for programming. Simulation and synthesis task has been performed on Xilinx Vivado v2021.1 IDE. the results exhibit high-rate encryption of 68 Gb/s and low energy consumption of 7 pJ/bit.

关键词： Ciphers Energy consumption Power demand Software algorithms Signal processing algorithms throughput Hardware

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Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems : A Vedic Mathematics Approach

Implementation and Performance Evaluation of Novel Line Adde...

引用

IEEE Region 10 international conference TENCON

作者： Sudhanshu Janwadkar Rasika Dhavse Sardar Vallabhbhai National Institute of Technology Surat India

ISBN: (数字)9781728184555

ISBN: (纸本)9781728184562

In this paper, we propose design and implementation of novel line adder architecture capable of adding multiple addends in a single step. the architecture is derived based on addition algorithm from Shuddha system of vedic mathematics. the adder architecture is particularly suitable for a class of applications, such as FIR filter, where multiple operands are required to be added. the implementation is particularly suited for portable systems where area and power consumption are highly constrained. We then quantitatively compare proposed adder architecture against popular parallel-prefix adder architectures for different wordlengths (N = 4, 8, 16 and 32 bits). All the architectures are implemented on Genesys2 board (Xilinx part number xc7k325t-2ffg900c) using VHDL coding and Xilinx Vivado 2016.2 platform. Standard performance metrics such as FPGA device utilization (number of slices and logic LUTs), Power Consumption and Performance are considered for comparison. Results indicate that proposed vedic adder occupies 35.12 % lesser logic LUTs and 28.71 % lesser slices than any other adder architectures, under consideration, while at the same time, there is an improvement of 9.1 % in on-chip FPGA power consumption than all other adder architectures. the performance of vedic adder architecture draws parallel with that of fastest prefix adder being considered.

关键词： Adders Computer architecture Logic gates Mathematics Field programmable gate arrays Signal processing algorithms Power demand

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Compiling HPC Kernels for the REDEFINE CGRA

Compiling HPC Kernels for the REDEFINE CGRA

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Kavitha T. Madhu Saptarsi Das Nalesh S. S. K. Nandy Ranjani Narayan CAD Laboratory Indian Institute of Science Bangalore Morphing Machines Pvt. Ltd. Bangalore

In this paper, we present a compilation flow for HPC kernels on the REDEFINE coarse-grain reconfigurable architecture (CGRA). REDEFINE is a scalable macro-dataflow machine in which the compute elements (CEs) communicate through messages. REDEFINE offers the ability to exploit high degree of coarse-grain and pipeline parallelism. the CEs in REDEFINE are enhanced with reconfigurable macro data-paths called HyperCells that enable exploitation of fine-grain and pipeline parallelism at the level of basic instructions in static dataflow order. Application kernels that exhibit regularity in computations and memory accesses such as affine loop nests benefit from the architecture of HyperCell [1], [2]. the proposed compilation flow aims at exposing high degree of parallelism in loop nests in HPC application kernels using polyhedral analysis and generates meta-data to effectively utilize the computational resources in HyperCells. Memory is explicitly managed through compiler's assistance. We address the compilation challenges such as partitioning with load balancing, mapping and scheduling computations and management of operand data while targeting multiple HyperCells in the REDEFINE architecture. the proposed solution scales well meeting the performance objectives of HPC computing.

关键词： Kernel parallel processing Pipelines Synchronization Computer architecture Bandwidth Fabrics

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