A technique for the design rule verification of layouts composed of library cells is presented. Instead of directly manipulating mask geometries, DRC correctness is tied to a set of user defined patterns of allowed ce...
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A technique for the design rule verification of layouts composed of library cells is presented. Instead of directly manipulating mask geometries, DRC correctness is tied to a set of user defined patterns of allowed cell interactions called templates. Design rule verification is achieved by covering the layout withthese templates. Both layouts and templates are defined in terms of graphs and all operations are performed in the graph domain. the verification procedure is incremental and because the number of cell instances is much smaller than the number of mask geometries it is much faster than techniques that directly manipulate mask geometries.< >
An electron beam (EB) data conversion system for a character projection (CP) writing method has been constructed. the system has been developed based on an EB data conversion system for a variable-shaped beam (VSB), a...
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An electron beam (EB) data conversion system for a character projection (CP) writing method has been constructed. the system has been developed based on an EB data conversion system for a variable-shaped beam (VSB), and a formatting module for CP writing was added. In addition, several functions have been developed to analyze CP writing patterns, and combined withthe system. the functions aim to select the CP writing patterns that best reduce writing time and to achieve the highest throughput. the new system was applied to a real LSI pattern to test the conversion function and to estimate the conversion speed. A model pattern of a 1 Gbit dynamic random access memory was successfully converted to EB data format. the conversion processing time was less than 14 min for each layer.
Reducing communication overhead has been widely recognized as a requirement for achieving efficient mappings which substantially reduce the execution time of parallelalgorithms. this paper presents an iterative heuri...
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the systolic screen is a very natural parallel architecture for image processing. A square root n∗ square root n systolic screen consists of a square root n∗ square root n mesh-of-processors with each processor repres...
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the author introduces the use of data duplication in massively parallelarchitectures as a tool for improving the running time of the basic data movement operations. He demonstrates its use by presenting two algorithm...
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We consider the problem of partitioning coarse grain signal flow graphs for execution on a class of hierarchically structured, heterogeneous multiprocessor architectures tailored to match the characteristics of a spec...
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Several algorithms are discussed for implementing global combine (summation) on distributed memory computers using a two-dimensional mesh interconnect with wormhole routing. these include algorithmsthat are asymptoti...
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In our earlier papers, the parallelization and implementations of Gauss-Seidel (G-S) algorrthms for power flow analysis have been investigated on a Sequent flnlnnce ahared memory (SM) machine. In this paper, we genera...
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In the field of parallelprocessing, there is a great diversity of languages and architectures which become obsolete at a rapid pace. In this environment, portability is an important issue. Unfortunately, most paralle...
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Flynn classified high speed (parallel) computers into four categories. Of these, the single instruction stream, multiple data stream (SIMD) processor array machines have become very popular in practical parallel proce...
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