检索结果-内蒙古大学图书馆

Mobile Networks and Wireless Communications (ICMNWC), IEEE international conference on

作者： Sonali Karale Jatinderkumar R. Saini School of Computer Science and IT Jain (Deemed-to-be University) Bangalore India Symbiosis Institute of Computer Studies and Research Symbiosis International (Deemed University) Pune India

ISBN: (数字)9798331528348

ISBN: (纸本)9798331528355

One of the prime research areas today is video summarisation, where the short summary of the input video is generated. the output video content is based on the object of interest. It also saves the time of the viewer; they won't need to view the entire long duration video. To do this process faster, the redundant or steady frames need to be removed first. Background subtraction is one of the techniques used to identify moving objects by calculating the difference between previous and current frame. In our research paper, we have used KNN, MOG2 and CNT for the BGS methods. We have also used different YOLO model like YOLOv3, YOLOv5, YOLOv7 and YOLOv8 to generate annotations file and use them for measuring the performance of the BS algorithms. these methods are implemented using parallel processing approach to process more than one video at a time. the performance analysis of these methods is done based on the time of execution and precision. the experiment result shows that the KNN with YOLOv7 perform better and parallel processing approach speedup the execution.

关键词： YOLO Wireless communication Analytical models Instruction sets Nearest neighbor methods parallel processing Time measurement Libraries Performance analysis Object recognition

来源：评论

学校读者我要写书评

暂无评论

Research and Implementation of parallel Data Acquisition System for Inertial Sensor Array

Research and Implementation of Parallel Data Acquisition Sys...

引用

IEEE international conference on Electronic Information and Communication Technology (ICEICT)

作者： Haomiao Jiang Du Chen Haile Bai Gang Li Xiaoliang Luo Zhe Ji Guangjun Wen Yongjun Huang School of Information and Communication Engineering University of Electronic Science and Technology of China Chengdu China Academy of Military Science PLA National Innovation Institute of Defense Technology Beijing China

ISBN: (数字)9798350384437

ISBN: (纸本)9798350384444

Arrays can improve the performance of inertial sensors, but the lack of synchronization in acquisition times among sensors is a significant challenge. To address this issue, a data acquisition system has been developed that uses parallel I2C and SPI buses to enhance measurement precision. this study compares the impact of serial and parallel bus architectures and sensor quantity on the efficacy of inertial sensor arrays. the performance indices used for evaluation include zero bias, zero bias stability, and Allan variance. the experiment indicates that the parallel bus significantly enhances the zero bias stability of the sensors. the incorporation of additional sensors reduces stochastic errors, such as angle random walk, quantization noise, and zero bias. the use of a parallel bus configuration enables easy expansion of the sensor count within the array, thereby significantly enhancing the applicative merit of the inertial sensor array.

关键词： Quantization (signal) Protocols Inertial sensors Data acquisition Stability criteria Noise Synchronization

来源：评论

学校读者我要写书评

暂无评论

Quadrature Coupler with Enhanced Coupling Bandwidth and DC Isolation for C-Band Applications

Quadrature Coupler with Enhanced Coupling Bandwidth and DC I...

引用

international conference on Signal processing and Integrated Networks (SPIN)

作者： V. Nagisha V. Nivesha Madhur Deo Upadhayay Electrical Engineering Shiv Nadar University Gr Noida

ISBN: (数字)9781728154756

ISBN: (纸本)9781728154763

this paper presents an alternate design for a conventional 3dB Branch line coupler (Quadrature Coupler) for C Band applications. the proposed coupler is designed for 5.2GHz. the proposed coupler has parallel-coupled lines at the port of conventional 3dB coupler with slotted ground plane. the novel design of the coupler allows 82.6% of bandwidth improvement with DC(Direct Current) isolation. the designs have been simulated and fabricated on FR4 dielectric substrate and measured using Vector Network Analyzer. Simulated and fabricated results of the S-parameters are presented.

关键词： Couplers Bandwidth Power transmission lines Couplings Scattering parameters Impedance Signal processing

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation Of a High throughput Low Power Advanced Encryption Standard (AES-128) Cipher

FPGA Implementation Of a High Throughput Low Power Advanced ...

引用

international conference on Signal processing and Integrated Networks (SPIN)

作者： Jaideep Kala Jeebananda Panda Lavi Tanwar Department of Electronics and Communication Delhi Technological University New Delhi India

Ensuring secure transmission and storage of digital information is critical for any organization to function properly. To address this issue, encryption algorithms are commonly used. Advanced Encryption Standard (AES) has been globally adopted as the mainstay cipher algorithm for securing transmission networks and storage devices due to its easy implementation and compatibility with both hardware and software applications. Another reason for its widespread popularity is its uncompromisable nature against existing brute force attacks, making it practically unbreakable on existing computing power. AES implementation for battery operated devices requires an algorithm with low power consumption and high-speed encryption/decryption of digital data. this paper proposes an FPGA implementation of a high throughput parallel pipelined 128-bit AES algorithm with a low power key expansion mechanism for iterative stages. A 128-bit symmetric key has been used for undertaking 10 rounds of transformations. All the encryption and decryption transformations are simulated using iterative design methodology in order to minimize hardware consumption. Xilinx Artix-7 FPGA device is used for hardware evaluation and Verilog HDL for programming. Simulation and synthesis task has been performed on Xilinx Vivado v2021.1 IDE. the results exhibit high-rate encryption of 68 Gb/s and low energy consumption of 7 pJ/bit.

关键词： Ciphers Energy consumption Power demand Software algorithms Signal processing algorithms throughput Hardware

来源：评论

学校读者我要写书评

暂无评论

An approximation algorithm for scheduling dependent tasks on m processors with small communication delays

An approximation algorithm for scheduling dependent tasks on...

引用

international conference on Emerging Technologies and Factory Automation (ETFA)

作者： C. Hanen A. Munier LITP IBP Université Pierre et Marie Curie Paris France

this paper defines and studies an approximation algorithm for scheduling tasks with small communication delays on parallel processors. In a first step, a schedule for the relaxed problem instance with an unlimited number of processors is generated. then this solution is used to solve the resource conflicts during the scheduling phase on m processors, with a rather unusual feature: a feasible task may be tactically delayed, even inducing idleness on a processor in order to wait for a more important task. the relative worst case performance of this algorithm is analysed with respect to the ratio between communication times and processing times and to the performance of the relaxed solution. It improves significantly the best known performance ratio of an algorithm for this problem (7/3 against 3).

关键词： Approximation algorithms Scheduling algorithm Processor scheduling Clustering algorithms Performance analysis Algorithm design and analysis parallel architectures Delay systems

来源：评论

学校读者我要写书评

暂无评论

Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems : A Vedic Mathematics Approach

Implementation and Performance Evaluation of Novel Line Adde...

引用

IEEE Region 10 international conference TENCON

作者： Sudhanshu Janwadkar Rasika Dhavse Sardar Vallabhbhai National Institute of Technology Surat India

ISBN: (数字)9781728184555

ISBN: (纸本)9781728184562

In this paper, we propose design and implementation of novel line adder architecture capable of adding multiple addends in a single step. the architecture is derived based on addition algorithm from Shuddha system of vedic mathematics. the adder architecture is particularly suitable for a class of applications, such as FIR filter, where multiple operands are required to be added. the implementation is particularly suited for portable systems where area and power consumption are highly constrained. We then quantitatively compare proposed adder architecture against popular parallel-prefix adder architectures for different wordlengths (N = 4, 8, 16 and 32 bits). All the architectures are implemented on Genesys2 board (Xilinx part number xc7k325t-2ffg900c) using VHDL coding and Xilinx Vivado 2016.2 platform. Standard performance metrics such as FPGA device utilization (number of slices and logic LUTs), Power Consumption and Performance are considered for comparison. Results indicate that proposed vedic adder occupies 35.12 % lesser logic LUTs and 28.71 % lesser slices than any other adder architectures, under consideration, while at the same time, there is an improvement of 9.1 % in on-chip FPGA power consumption than all other adder architectures. the performance of vedic adder architecture draws parallel with that of fastest prefix adder being considered.

关键词： Adders Computer architecture Logic gates Mathematics Field programmable gate arrays Signal processing algorithms Power demand

来源：评论

学校读者我要写书评

暂无评论

Prototyping of Low-Cost Configurable Sparse Neural processing Unit with Buffer and Mixed-Precision Reshapeable MAC Array

Prototyping of Low-Cost Configurable Sparse Neural Processin...

引用

international conference on parallel and Distributed Systems (ICPADS)

作者： Binyi Wu Wolfgang Furtner Bernd Waschneck Christian Mayr Faculty of Electrical and Computer Engineering Technische Universit¨at Dresden Dresden Germany Division of Power and Sensor Systems Infineon Technologies Munich Germany Centre for Tactile Internet with Human-in-the-loop (CeTI) Technische Universität Dresden Dresden Germany

More recently, it has become possible to run deep learning algorithms on edge devices such as microcontrollers due to continuous improvements in neural network optimization algorithms such as quantization and neural architecture search. Nonetheless, most of the embedded hardware available today still falls short of the requirements of running deep neural networks. As a result, specialized processors have emerged to improve the inference efficiency of deep learning algorithms. However, most are not for edge applications that require efficient and low-cost hardware. therefore, we design and prototype a low-cost configurable sparse Neural processing Unit (NPU). the NPU has a built-in buffer and a reshapable mixed-precision multiply-accumulator (MAC) array. the computing and memory resources of the NPU are parameterized, and different NPUs can be derived. Besides, users can also conFigure the NPU at runtime to fully utilize the resources. In our experiments, the 200MHz NPU with only 32 MACs is more than 32 times faster than the 400MHzSTM32H7 when inferring MobileNet-Vl. Besides, the yielded NPUs can achieve roofline or even beyond roofline performance. the buffer and reshapeable MAC array push the NPU’s attainable performance to the roofline, while the feature of supporting sparsity allows the NPU to obtain performance beyond the roofline.

关键词： Deep learning Runtime Quantization (signal) Program processors Neural networks Random access memory Prototypes

来源：评论

学校读者我要写书评

暂无评论

Delay Margin Analysis of a Large-Scale Optimal Velocity Model using the parallel processing Delay Margin Finder (parDMF)

Delay Margin Analysis of a Large-Scale Optimal Velocity Mode...

引用

international conference on Control, Decision and Information Technologies (CoDIT)

作者： Duo Wang Adrián Ramírez Rifat Sipahi Northeastern University Boston MA USA Cátedras CONACYT México Division of Applied Mathematics IPICYT México

ISBN: (数字)9781728159539

ISBN: (纸本)9781728159546

A connected vehicle model with delays due to human reaction times and sensing and communication lines is considered. In particular, we investigate how time delays affect the equilibrium stability of this model in large scale. We focus mainly on the delay margin (DM) of this equilibrium, i.e., the largest delay that the system can accommodate without losing stability. We present how DM is influenced by the sparsity of sensor and communication lines and the number of vehicles. Different from previous work, no assumption is imposed on the structure of the network topology; the large-scale dynamics is treated in a computationally efficient manner by utilizing our recently developed parallel processing computational tool Delay Margin Finder (parDMF).

关键词： Delays Stability analysis Mathematical model Connected vehicles Vehicle dynamics Analytical models Microscopy

来源：评论

学校读者我要写书评

暂无评论

Using a multitasking GPU environment for content-based similarity measures of big data

引用

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2013年 7971卷 181-196页

作者： Tarakji, Ayman Hassani, Marwan Lankes, Stefan Seidl, thomas RWTH Aachen University Aachen Germany Data Management and Data Exploration Group RWTH Aachen University Germany

ISBN: (纸本)9783642396366

Performance and efficiency became recently key requirements of computer architectures. Modern computers incorporate Graphics processing Units (GPUs) into running data mining algorithms, as well as other general purpose computations. In this paper, different parallelization methods are analyzed and compared in order to understand their applicability. From multi-threading on shared memory to using NVIDIA's GPU accelerators for increasing performance and efficiency on parallel computing, this work discusses the parallelization of data mining algorithms considering performance and efficiency issues. the performance is compared on both many-core systems and GPU accelerators on a distance measure algorithm using a relatively big data set. We optimize the way we deal with GPUs in heterogeneous systems to make them more suitable for big data mining applications with heavy distance calculations. Moreover, we focus on achieving a higher utilization of GPU resources and a better reuse of data. Our implementation of the content-based similarity algorithm SQFD on the GPU outperforms by up to 50 x CPU counterparts, and up to 15x CPU multi-threaded implementations. © Springer-Verlag Berlin Heidelberg 2013.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Distributed Deep Learning with Data parallelism for Diabetic Retinopathy Classification 1

引用

7th international conference on Smart Trends in Computing and Communications, SmartCom 2023

作者： Patil, Sanskruti S. Patil, Mahesh S. Chickerur, Satyadhyan Giraddi, Shantala Shahapur, Seetharam N. Hadalageri, Anup School of Computer Science and Engineering KLE Technological University Karnataka Hubballi580031 India Center for High Performance Computing KLE Technological University Karnataka Hubballi580031 India

ISBN: (数字)9789819907694

ISBN: (纸本)9789819907687

the large-scale model training is typically slower and necessitates high-performance workstations and Distributed Deep Learning (DDL). the DDL models trained on a massive volume of data can outperform single accelerators being used, i.e., the performance of deep learning (DL) models can be enhanced by using distributed and parallel deep learning methods. But the DDL models need to be redesigned and evaluated for particular hardware resources and applications, requiring the literature on various DDL model evaluations for assistance. Authors in the proposed work design and evaluate DDL with data parallelism for classifying Diabetic retinopathy (DR) images. A performance comparative study on the DDL strategy implemented on DenseNet is presented where the model is trained on multi-GPUs with counts from 1 to 8. the results show that the model takes less time when trained on multi-GPUs compared to single GPU. the detailed evaluation analysis of DDL with data parallelism is presented in this paper. © 2023, the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：