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检索条件"任意字段=7th International Conference on Algorithms and Architectures for Parallel Processing"

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Proceedings of the international conference on Supercomputing

Proceedings of the International Conference on Supercomputin...

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7th international conference on Supercomputing, ICS 1993

ISBN: (纸本)089791600X

the proceedings contain 43 papers. the topics discussed include: graph contraction for physical optimization methods: a quality-cost tradeoff for mapping data on parallel computers;managing pages in shared virtual memory systems: getting the compiler into the game;the EM-4 under implicit parallelism;data stream control optimization in dataflow architectures;the effectiveness of decoupling;speculative prefetching;increasing the instruction fetch rate via multiple branch prediction and a branch address cache;speculative execution and branch prediction on parallel machines;and PARADIGM: a compiler for automatic distribution on multicomputers.

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parallel implementation of the rational fraction polynomial method

Parallel implementation of the rational fraction polynomial ...

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Proceedings of the 11th international Modal Analysis conference. Part 1 (of 2)

作者： Newman, N.D. Friswell, M.I. Penny, J.E.T. Aston Univ Birmingham United Kingdom

ISBN: (纸本)0912053410

the trend in modal extraction algorithms is to use all the available FRF data to obtain a global estimate of the natural frequencies, damping ratios and mode shapes. Improvements in transducer and signal processing technology allow the simultaneous measurement of many hundreds of channels of response data. the quality of data available and the complexity of the extraction algorithms make considerable demands on the available computer power and require a fast PC or work station to perform satisfactorily. An alternative to ever faster sequential processors is to implement the algorithm in parallel, for example on a network of transputers. parallel architectures are a cost effective means of increasing computational power, and a large number of response channels simply require more processors. this paper considers how one typical modal extraction algorithm, the Rational Fraction Polynomial Method, may be implemented on a network of transputers. the Rational Fraction Polynomial Method is a frequency domain curve fitting algorithm and is one of the easiest algorithms to convert to parallel computation. this paper reviews the algorithm and considers the problems involved in a parallel implementation.

关键词： Structural analysis

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Performance prediction of parallel processing systems: the PAMELA methodology 93

Performance prediction of parallel processing systems: The P...

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7th international conference on Supercomputing, ICS 1993

作者： Van Gemund, Arjan J.C. Faculty of Electrical Engineering Delft University of Technology P.O. Box 5031 GA DelftNL-2600 Netherlands

ISBN: (纸本)089791600X

In this paper we present a new methodology for the performance prediction of parallel programs on parallel platforms ranging from shared-memory to distributed-memory (vector) machines. the methodology comprises a procedural program and machine specification paradigm based on PAMELA (PerformAnce ModEling LAnguage), along with a performance calculus, called "serialization analysis". this calculus extends conventional parallel program analysis technology by explicitly accounting for resource contention, yet. at the low evaluation cost typical for static techniques. It is shown that, where conventional techniques introduce fundamental errors, predictions from serialization analysis remain realistic. Apart from the merits of the methodology itself, this high reliability/cost ratio makes PAMELA an attractive candidate for compile-time application within the performance prediction hierarchy often found in parallel programming environments. © 1993 ACM.

关键词： Modeling languages

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parallel processing architecture for the hitachi S-3800 shared-memory vector multiprocessor 93

Parallel processing architecture for the hitachi S-3800 shar...

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7th international conference on Supercomputing, ICS 1993

作者： Kitai, Katsuyoshi Isobe, Tadaaki Tanaka, Yoshikazu Tamaki, Yoshiko Fukagawa, Masakazu Tanaka, Teruo Inagami, Yasuhiro Central Research Laboratory Hitachi Ltd. 1-280 Higashi-koigakubo Kokubunji Tokyo185 Japan General Purpose Computer Division Hitachi Ltd. 1 Horiyamashita Hadano Kanagawa259-13 Japan

ISBN: (纸本)089791600X

this paper discusses the architecture of the new Hitachi supercomputer series, which is capable of achieving 8 GFLOPS in each of up to four processors. this architecture provides high-performance processing for fine-grain parallelism, and it allows efficient parallel processing even in an undedicated environment. It also features the newly-developed time-limited spin-loop synchronization, which combines spin-loop synchronization with operating system primitives, and a communication buffer (CB) which caches shared variables for synchronization, thus allowing them to be accessed faster. three new instructions take advantage of the CB in order to reduce the parallel overhead. the results of performance measurements confirm the effectiveness of the CB and the new instructions. © 1993 ACM.

关键词： Synchronization

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7th international Symposium on Methodologies for Intelligent Systems, ISMIS 1993

7th International Symposium on Methodologies for Intelligent...

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7th international Symposium on Methodologies for Intelligent Systems, ISMIS 1993

ISBN: (纸本)9783540568049

the proceedings contain 60 papers. the special focus in this conference is on Methodologies for Intelligent Systems. the topics include: On extended disjunctive logic programs;model finding strategies in semantically guided instance-based theorem proving;an expressive three-valued logic with two negations;compiling proof search in semantic tableaux;short CNF in finitely-valued logics;a modal approach;an admissible heuristic search algorithm;building an expert system language interpreter with the rule network technique;input-driven control of rule-based expert systems;case-based planning for medical diagnosis;a methodology for expert systems development;towards intelligent databases;combining classification and nonmonotonic inheritance reasoning;mechanical proof systems for logic ii, consensus programs and their processing;the logic of only knowing as a unified framework for non-monotonic reasoning;terminological logic involving time and evolution;knowledge management by example;system reorganization and load balancing of parallel database rule processing;using semantic information for processing negation and disjunction in logic programs;methodologies for knowledge-based software engineering;updating logic programs;expressing program requirements using refinement lattices;finding logical consequences using unskolemization;controlled explanation systems;a liftable meta-logic for multiple-valued logics;text-based and fuzzy-centered architectures;boolean reasoning for decision rules generation;upper and lower entropies of belief functions using compatible probability functions;reasoning about higher order uncertainty in possibilistic logic and approximation methods for knowledge representation systems.

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Processor assignment in heterogeneous message passing parallel architectures 26

Processor assignment in heterogeneous message passing parall...

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26th Hawaii international conference on System Sciences, HICSS 1993

作者： Porto, S.C.S. Menasce, D.A. Univ. Federal Fluminense Niteroi RJ24210 Brazil PUC-RIO Rio de Janeiro RJ22453 Brazil Dept. of Computer Science George Mason University FairfaxVA22030-4444 United States

ISBN: (纸本)0818632305

Cost-effective multiprocessor designs may be obtained by combining processors of different speeds (heterogeneous architecture) in the same architecture. this way, the serial and critical portions of the application may benefit from a fast single processor. the observed trend in the supercomputing industry indicates that future generations of high speed machines will be built by combining few very fast processors with hundreds or even thousands of slower identical VLSI processors, interconnected through a message passing scheme. Scheduling algorithms for such environments should be designed an order for applications to benefit from the heterogeneity aspect of the architecture. At the same time, the presence of communication delays in the task scheduling problem determines that two opposite criteria must be considered: Communications costs and processor load. this paper proposes novel staiic heuristic processor assignment algorithms for heterogeneous message passing architectures and discusses their performance through the use of Markov chain based models. the execution time of diflerent parallel applications is computed as a function of the degree of heterogeneity of the architecture, the application communication/processing ratio, and of the fraction of sequential processing. © 1993 IEEE.

关键词： Message passing

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A high-performance parallel database architecture 93

A high-performance parallel database architecture

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7th international conference on Supercomputing, ICS 1993

作者： Leung, C.H.C. Ghogomu, H.T. Computer Science Department Birkbeck College University of London Malet Street LondonWC1E 7HX United Kingdom

ISBN: (纸本)089791600X

A high-performance parallel system for processing databases is presented, which adopts a distributed memory architecture and has been successfully implemented on a transputer platform. In addition to developing and implementing a variety of rules and schemes for parallelizing database queries, general analytic models for distributed memory database processing have been formulated, which have been successfully validated against measurements. Experimental data also indicate that the system is able to attain near linear speedup for the join operation. We also demonstrate that a linear speedup is unattainable for distributed memory database systems, and an upper bound governing the maximum transaction rate is derived. the present system is also reconfigurable and adopts a novel processor allocation scheme based on equalizing the elapsed time among different cooperating processors, which is able to readjust the processing resoufces assigned to particular database tasks in accordance with changing demands on the system. © 1993 ACM.

关键词： Memory architecture

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16th IFIP Working Group 7.3 international Symposium on Computer Performance Modeling, Measurement and Evaluation and ACM SIGMETRICS conference on Measurement and Modeling of Computer Systems, 1993

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16th IFIP Working Group 7.3 international Symposium on Computer Performance Modeling, Measurement and Evaluation and ACM SIGMETRICS conference on Measurement and Modeling of Computer Systems, 1993

ISBN: (纸本)9783540572978

the proceedings contain 26 papers. the special focus in this conference is on Computer Performance Modeling, Measurement and Evaluation. the topics include: parallel simulation;properties and analysis of queueing network models with finite capacities;performance analysis and optimization with the power-series algorithm;multiprocessor and distributed system design;response time distributions in queueing network models;fast simulation of rare events in queueing and reliability models;an inlxoduction to modeling dynamic behavior with time series analysis;issues in trace-driven simulation;maximum entropy analysis of queueing network models;performance modeling using DSPN express;relaxation for massively parallel discrete event simulation;an overview of tes processes and modeling methodology;performance engineering of client-server systems;queueing networks with finite capacities;performance instrumentation techniques for parallel systems;a survey of bottleneck analysis in closed networks of queues;software performance engineering;performance measurement using system monitors;providing quality of service packet switched networks;dependability and performability analysis;architectures and algorithms for digital multimedia on-demand servers;analysis and control of polling systems;modeling and analysis of transaction processing systems.

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EMC-Y: parallel processing element optimizing communication and computation 93

EMC-Y: Parallel processing element optimizing communication ...

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7th international conference on Supercomputing, ICS 1993

作者： Kodama, Yuetsu Koumura, Yasuhito Sato, Mitsuhisa Sakane, Hirohumi Sakai, Shuichi Yamaguchi, Yoshinori Electrotechnical Laboratory Japan SANYO Electric Co. Ltd. Japan Real World Computing Partnership Japan

ISBN: (纸本)089791600X

EMC-Y is a new processing element for highly parallel computers designed to achieve high performance parallel computation by fusing a dataflow mechanism and a von Neumann execution pipeline. We have already developed EMC-R, which is the processing element used in the EM-4 prototype. EMC-Y improves on EMC-R's packet communication performance, allowing it to tolerate a more network traffic. this paper presents the architecture of EMC-Y, concentrating on the principles of packet communication. EMC-Y uses an output packet buffer and optimal packet routing to improve the performance of packet sending and transferring. EMC-Y changes the memory access priority for input packet buffer operation to improve the performance of receiving packets. Since the EMC-Y processor not only improves the performance of packet input and output but also balances them, it can tolerate a large amount of traffic and can improve the execution performance. We evaluate the improvements of EMC-Y architecture using a clock level simulator. the results show that EMC-Y improves performance by 50% to 70% in several programs over EMC-R at the same clock speed. © 1993 ACM.

关键词： Network architecture

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PYRAMIDAL NEURO-VISION ARCHITECTURE FOR VISION MACHINES 12

PYRAMIDAL NEURO-VISION ARCHITECTURE FOR VISION MACHINES

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12th conference on Intelligent Robots and Computer Vision: algorithms and Techniques

作者： GUPTA, MM KNOPF, GK UNIV SASKATCHEWAN COLL ENGNINTELLIGENT SYST RES LABSASKATOON S7N 0W0SASKATCHEWANCANADA

ISBN: (纸本)0819413208

the vision system employed by an intelligent robot must be active; active in the sense that it must be capable of selectively acquiring the minimal amount of relevant information for a given task. An efficient active vision system architecture that is based loosely upon the parallel-hierarchical (pyramidal) structure of the biological visual pathway is presented in this paper. Although the computational architecture of the proposed pyramidal neuro-vision system is far less sophisticated than the architecture of the biological visual pathway, it does retain some essential features such as the converging multilayered structure of its biological counterpart. In terms of visual information processing, the neuro-vision system is constructed from a hierarchy of several interactive computational levels, whereupon each level contains one or more nonlinear parallel processors. Computationally efficient vision machines can be developed by utilizing both the parallel and serial information processing techniques within the pyramidal computing architecture. A computer simulation of a pyramidal vision system for active scene surveillance is presented.

关键词： Machine vision Visualization Robot vision Signal processing Computer vision technology Computer architecture Computing systems Data processing Information visualization Content addressable memory

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