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Speculative execution and branch prediction on parallel machines 93

Speculative execution and branch prediction on parallel mach...

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7th international conference on Supercomputing, ICS 1993

作者： theobald, Kevin B. Gao, Guang R. Hendren, Laurie J. McGill University School of Computer Science 3480 University St. McConnell MontréalQCH3A 2A7 Canada

ISBN: (纸本)089791600X

Several recent studies on the limits of parallelism have reported that speculative execution can substantially increase the amount of exploitable parallelism in programs, especially non-numerical programs. this is true even for parallel machines models which allow multiple flows of control. However, most architectural techniques for speculation and branch prediction are geared toward conventional computers with a single flow of control, and little has been done in studying speculation models and techniques for parallel machines with multiple threads of control. this paper presents a model of speculative execution for parallel machines. We define two different types of speculation (conservative and aggressive), and define the level of speculation (how far ahead the speculation can go). We then show how to modify conventional methods of branch and jump prediction to work with this model. this paper also presents a comprehensive quantitative study of: (1) how parallelism is affected by the speculative execution and branch prediction techniques under a parallel model of execution, and (2) what speculation depth is required to get a large portion of available parallelism. We measure the parallelism limits of 5 long benchmarks (4 non-numerical) with different speculation models and branch prediction methods, and compare the results. © 1993 ACM.

关键词： parallel architectures

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4th international conference on Foundations of Data Organization and algorithms, FODO 1993

4th International Conference on Foundations of Data Organiza...

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4th international conference on Foundations of Data Organization and algorithms, FODO 1993

ISBN: (纸本)9783540573012

the proceedings contain 27 papers. the special focus in this conference is on Foundations of Data Organization and algorithms. the topics include: Storage system architectures for continuous media data;physical storage organizations for time-dependent multimedia data;user interface management system embedded in a multimedia document editor framework;management of physical replicas in parallel multimedia information systems;efficient similarity search in sequence databases;filtered hashing;design and implementation of DDH: a distributed dynamic hashing algorithm;performance analysis of superimposing-coded signature files;trie methods for representing text;estimation of false drops in set-valued object retrieval with signature files;data structure and algorithms for new hardware technology;evaluation of upper bounds and least nodes as database operations;a system for data sharing among heterogeneous object models;dynamic selectivity estimation for multidimensional queries;reducing page thrashing in recursive query processing;the sybase replication server project;analogical inferred compensation method for heterogeneous database schema mismatch and its application to hypermedia cooperative work system;a survey of DBMS research issues in supporting very large tables;a survey of DBMS research issues in supporting very large tables;an algorithm for the implementation of replicated tables;improved traditional mirror;adaptive load balancing in disk arrays;challenges to the database community;an object-oriented office space description model and an office view management mechanism for distributed office environment and stamp locking method for multiversion composite objects.

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A static parameter based performance prediction tool for parallel programs 93

A static parameter based performance prediction tool for par...

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7th international conference on Supercomputing, ICS 1993

作者： Fahringer, thomas Zima, Hans P. University of Vienna Department of Software Technology and Parallel Systems Brünner Str. 72 ViennaA-1210 Austria

ISBN: (纸本)089791600X

this paper presents a Parameter based Performance Prediction Tool (PPPT) which is part of the Vienna Fortran Compilation System (VFCS), a compiler that automatically translates Fortran programs into message passing programs for massively parallel architectures. the PPPT is applied to an explicitly parallel program generated by the VFCS, which may contain synchronous as well as asynchronous communication and is attributed with parameters computed in a previous profiling run. It statically computes a set of optional parameters that characterize the behavior of the parallel program. this includes work distribution, the number of data transfers, the amount of data transferred, transfer times, network contention, and the number of cache misses. these parameters can be selectively determined for statements, loops, procedures, and the entire program;furthermore, their effect with respect to individual processors can be examined. the tool plays an important role in the VFCS by providing the system as well as the user with vital performance information about the program. In particular, it supports automatic data distribution generation and the intelligent selection of transformation strategies, based on properties of the algorithm and characteristics of the target architecture. the tool has been implemented. Experiments show a strong correlation between the statically computed parameters and actual measurements;furthermore it turns out that the predicted parameter values allow a realistic ranking of different program versions with respect to the actual runtime. © 1993 ACM.

关键词： Parameter estimation

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Super-threading: Architectural and software mechanisms for optimizing parallel computation 93

Super-threading: Architectural and software mechanisms for o...

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7th international conference on Supercomputing, ICS 1993

作者： Sakai, Shuichi Okamoto, Kazuaki Matsuoka, Hiroshi Hirono, Hideo Kodama, Yuetsu Sato, Mitsuhisa Massively Parallel Architecture Laboratory RWC Tsukuba Research Center Tsukuba Mitsui Building 1-6-1 Takezono Tsukuba Ibaraki305 Japan Computer Science Division Electrotechnical Laboratory 1-1-4 Umezono Tsukuba-shi Ibaraki305 Japan

ISBN: (纸本)089791600X

this paper presents super-threading, which generically means the architectural and software mechanisms for optimizing parallel computation. Super-threading includes architectural optimization of a processing element (PE), mechanisms for supporting fast communication and computation, techniques of a compiler and a run time system for optimizing thread creation, thread allocation, tuning of granularity and data allocation to physically distributed storage. this paper states what super-threading is and examines some of the technologies belonging to it. the processor architecture based on super-threading is proposed and its implementation on a highly parallel computer EM-4 is shown with performance data. Software issues about super-threading are also examined mainly from the viewpoint of granularity optimization. Dynamic granularity optimization methods are proposed here, and evaluated on EM-4. the performance data indicate that super-threading is a key technology for realizing an efficient massively parallel computer. © 1993 ACM.

关键词： Digital storage

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System reorganization and load balancing of parallel database rule processing 7th

System reorganization and load balancing of parallel databas...

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7th international Symposium on Methodologies for Intelligent Systems, ISMIS 1993

作者： Dewan, Hasanat M. Stolfo, Salvatore J. Department of Computer Science Columbia University New YorkNY10027 United States

ISBN: (纸本)9783540568049

In the coming decade, high-speed network computing using processors that are orders of magnitude faster than the platforms available today, will enable the integration and coalescing of vast amounts of information stored in diverse databases. this will provide unprecedented new opportunities for acquzrmg new knowledge by applying various inferential processes against such massive databases. Meeting this challenge requires significant advances in our understanding of how to build efficient, high-performance knowledge-base systems targeted to run on a variety of parallel and distributed hardware architectures. We address these concerns in the context of the PARADISER distributed rule processing system. We present an approach that combines statically computed restrwtions on rule programs to partition the workload of rule evaluation among an arbitrary number of processing sites, and dynamic load balancing protocols that update and reorganize the distribution of workload at runtimeo Finally, we analyze the dynamic load balancing protocols in terms of efficiency and scalability criteria. © 1993, Springer Verlag. All rights reserved.

关键词： HIgh speed networks

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Graph contraction for physical optimization methods: A quality-cost tradeoff for mapping data on parallel computers 93

Graph contraction for physical optimization methods: A quali...

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7th international conference on Supercomputing, ICS 1993

作者： Mansour, N. Ponnusamy, R. Choudhary, A. Fox, G.C. Northeast Parallel Architectures Center Syracuse University 111 College Place SyracuseNY13244 United States Beirut University College Lebanon

ISBN: (纸本)089791600X

Mapping data to parallel computers aims at minimizing the execution time of the associated application. However, it can take an unacceptable amount of time in comparison with the execution time of the application if the size of the problem is large. In this paper, first we motivate the case for graph contraction as a means for reducing the problem size. We restrict our discussion to applications where the problem domain can be described using a graph (e.g., computational fluid dynamics applications). then we present a mapping-oriented parallel Graph Contraction (PGC) heuristic algorithm that yields a smaller representation of the problem to which mapping is then applied. the mapping solution for the original problem is obtained by a straight-forward interpolation. We then present experimental results on using contracted graphs as inputs to two physical optimization methods;namely, Genetic Algorithm and Simulated Annealing. the experimental results show that the PGC algorithm still leads to a reasonably good quality mapping solutions to the original problem, while producing a substantial reduction in mapping time. Finally, we discuss the cost-quality tradeoffs in performing graph contraction. © 1993 ACM.

关键词： Mapping

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the data-parallel categorical abstract machine 5th

The data-parallel categorical abstract machine

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5th international conference on parallel architectures and Languages Europe, PARLE 1993

作者： Hains, Gaétan Foisy, Christian Département d’Informatique et Recherche Opérationnelle Université de Montréal MontréalQCH3C 3J7 Canada

ISBN: (纸本)9783540568919

Data-parallel ML is proposed for compilation to a distributed version (DPCAM) of Cousineau, Curien and Mauny’s Categorical Abstract Machine. the DPCAM is a static network of CAMs which dynamically restrict the MIMD execution mode: nodes execute the same program and communicate only while executing the same function body. Programs violating this restriction or exhibiting unbounded spatial recursion abort or deadlock. the execution model thus defines a class of SPMD programs. With respect to syntax and types, DPML is Mini-ML enriched with localization and remote evaluation functions. Its values are arrays of size matching the DPCAM network and containing ML values. Pointwise functions, data-parallel primitives and systolic algorithms are easily programmed. To improve the language’s portability there is no automatic virtualization mechanism. Hence DPML is an intermediate target for more elaborate data-parallel languages, bridging the gap between direct source-language processor allocation and fully automatic allocation. © Springer-Verlag Berlin Heidelberg 1993.

关键词： Artificial intelligence

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Dynamic switching of coherent cache protocols and its effects on doacross loops 93

Dynamic switching of coherent cache protocols and its effect...

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7th international conference on Supercomputing, ICS 1993

作者： Matsumoto, Takashi Hiraki, Kei Department of Information Science University of Tokyo 7-3-1 Hongo Bunkyo-ku Tokyo113 Japan

ISBN: (纸本)089791600X

In multiprocessor systems, overheads caused by inter-processor communication and synchronization have been one of the largest obstacles for efficient execution of parallel programs. To reduce these overheads in shared-memory/shared-bus multiprocessors, we have proposed two hardware mechanisms: the Inter-Cache Snoop Control Mechanism (ICSCM), which dynamically switches snoop-protocols for improving shared-bus utilization, and the Mechanism for Integrated Synchronization and Communication (MISC), which extends ICSCM to support producer-consumer type synchronization efficiently. We have developed an execution-driven multiprocessor simulator for evaluating performance with these mechanisms. Simulation experiments on doacross loops show remarkable speed-ups by ICSCM/MISC mechanisms. Although the proposed mechanisms are originally implemented on a single shared-bus system, they are easily applicable to a clustered multiprocessing systems. the methods used in a clustered system are discussed. © 1993 ACM.

关键词： Synchronization

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Independent performance modeling of parallel architectures and algorithms

Independent performance modeling of parallel architectures a...

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international conference on Computing and Information (ICCI)

作者： E.E. Johnson Parallel Architecture Research Laboratories New Mexico State University USA

A key requirement for the effective use of multiprocessor systems in real-world applications is an ability to accurately predict the performance of a specific algorithm on a specific architecture. Such performance prediction tools assist the system designer in initially selecting, and then modifying, both the algorithm and the architecture to obtain acceptable performance. In this paper, we present a modeling approach that permits separate evaluation of algorithm and architecture performance with only a small number of "cross" parameters required to link the two models. An example application of this technique to a Gaussian elimination algorithm on two dissimilar multiprocessor architectures shows good agreement with actual performance figures obtained from measurement and simulation.< >

关键词： parallel architectures Computer architecture Computational modeling parallel processing System performance Predictive models Multiprocessing systems Algorithm design and analysis throughput Concurrent computing

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Connectionist modeling and parallel architectures 93

Connectionist modeling and parallel architectures

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Proceedings of the 7th international conference on Neural Information processing Systems

作者： Joachim Diederich Ah Chung Tsoi Neurocomputing Research Centre School of Computing Science Queensland University of Technology Brisbane Australia Department of Electrical and Computer Engineering University of Queensland St Lucia Queensland Australia

the introduction of specialized hardware platforms for connectionist modeling ("connectionist supercomputer") has created a number of research topics. Some of these issues are controversial, e.g. the efficient implementation of incremental learning techniques, the need for the dynamic reconfiguration of networks and possible programming environments for these machines.

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