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Research and Implementation of parallel Data Acquisition System for Inertial Sensor Array

Research and Implementation of Parallel Data Acquisition Sys...

引用

IEEE international conference on Electronic Information and Communication Technology (ICEICT)

作者： Haomiao Jiang Du Chen Haile Bai Gang Li Xiaoliang Luo Zhe Ji Guangjun Wen Yongjun Huang School of Information and Communication Engineering University of Electronic Science and Technology of China Chengdu China Academy of Military Science PLA National Innovation Institute of Defense Technology Beijing China

ISBN: (数字)9798350384437

ISBN: (纸本)9798350384444

Arrays can improve the performance of inertial sensors, but the lack of synchronization in acquisition times among sensors is a significant challenge. To address this issue, a data acquisition system has been developed that uses parallel I2C and SPI buses to enhance measurement precision. this study compares the impact of serial and parallel bus architectures and sensor quantity on the efficacy of inertial sensor arrays. the performance indices used for evaluation include zero bias, zero bias stability, and Allan variance. the experiment indicates that the parallel bus significantly enhances the zero bias stability of the sensors. the incorporation of additional sensors reduces stochastic errors, such as angle random walk, quantization noise, and zero bias. the use of a parallel bus configuration enables easy expansion of the sensor count within the array, thereby significantly enhancing the applicative merit of the inertial sensor array.

关键词： Quantization (signal) Protocols Inertial sensors Data acquisition Stability criteria Noise Synchronization

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A low-cost fully pipelined architecture for fingerprint matching

A low-cost fully pipelined architecture for fingerprint matc...

引用

international conference on Signal processing Proceedings (ICSP)

作者： Jinwei Xu Jingfei Jiang Yong Dou Xiaolong Shen Science and Technology on Parallel and distributed Processing Laboratory National University of Defense Technology Changsha China

Fingerprint matching is a key procedure in fingerprint identification applications. the fingerprint-matching algorithm based on minutiae is one of the most typical algorithms that can achieve a reasonably correct recognition rate. Performance and cost are two critical factors when implementing minutia-based matching algorithms in most embedded applications. A low-cost, fully pipelined architecture for minutia-based fingerprint matching is proposed in this paper. A regular matching unit with a pipeline of 13 stages is designed as the core of the architecture, interfacing with a two-port RAM and a DDR3 controller. We implemented the whole architecture on a Xilinx FPGA board with the Virtex VII XC7VX485T chip. the matching unit can run with a frequency of 330 MHz on the chip, which leads the system to achieve a throughput of about 430000 fingerprints per second when processing typical datasets. the unit only occupies 568 slices, which is less than 1% of the available chip resources. the board only consumes 16 W of power when run. the architecture can gain about twice the throughput of the 2.93 GHz Intel Xeon5670 CPU at a low logic cost and power.

关键词： Fingerprint recognition throughput Random access memory Pipelines Computer architecture Field programmable gate arrays Algorithm design and analysis

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A fully digital Background calibration technique for pipeline analog-to-digital converters

A fully digital Background calibration technique for pipelin...

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international conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON

作者： Ziaeddin Koozeh Kanani Jafar Sobhi Mousa Yousefi Ahmad Tahmasebi Department of Electrical Engineering University of Tabriz Tabriz Iran Sarab Branch Islamic Azad University Sarab Iran

this paper describes a new background calibration technique for pipeline analog-to-digital converters (ADCs). the new scheme utilizes an existing digital foreground calibration algorithm and extends it to work in background. the goal is to digitally calibrate the pipeline ADCs in the background without stopping the input conversion. In this method one additional stage connected in parallel to the stage under calibration and one cyclic ADC are used to accommodate the calibration. the extra stage and the cyclic ADC are only used during the calibration process. Sources of error in pipeline architectures and effects of error on residue plot of 1-bit per stage are identified and discussed. the digital background calibration accounts for capacitor mismatch, comparator offset, charge injection and finite op-amp gain. By applying proposed calibration to a 12 bit resolution pipeline ADC, maximum INL improved from 14 to 0.6 LSB, and maximum DNL improved from 26 to 0.8 LSB.

关键词： Calibration Pipelines Analog-digital conversion Voltage Operational amplifiers Topology Signal processing algorithms Capacitors Signal resolution Aging

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Implementing a Pickup and Delivery Problem with Time Windows algorithm on a GPU cluster

Implementing a Pickup and Delivery Problem with Time Windows...

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international conference on Computer Sciences and Convergence Information Technology (ICCIT)

作者： Geeratiya Srimool Putchong Uthayopas Juta Pichitlamkhen Department of Computer Engineering Faculty of Engineering Kasetsart University Bangkok Thailand Department of Industrial Engineering Faculty of Engineering Kasetsart University Bangkok Thailand

this work presents an implementation of a high speed Pickup and Delivery Problem with Time Window (PDPTW) problem using GPU cluster. this problem represents a class of a major logistic problem. the software implemented is tested on 8 nodes GPU cluster equipped with two of Tesla M2050 (448 cores) card on each node. the result shows a speedup of nearly 7 times for a small problem and 43 times using 4 nodes for a large problem. In the presentation, some factors that affect the performance will be discussed.

关键词： Graphics processing unit Instruction sets Vehicles parallel processing Clustering algorithms Handheld computers

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Distributed Deep Learning with Data parallelism for Diabetic Retinopathy Classification 1

引用

7th international conference on Smart Trends in Computing and Communications, SmartCom 2023

作者： Patil, Sanskruti S. Patil, Mahesh S. Chickerur, Satyadhyan Giraddi, Shantala Shahapur, Seetharam N. Hadalageri, Anup School of Computer Science and Engineering KLE Technological University Karnataka Hubballi580031 India Center for High Performance Computing KLE Technological University Karnataka Hubballi580031 India

ISBN: (数字)9789819907694

ISBN: (纸本)9789819907687

the large-scale model training is typically slower and necessitates high-performance workstations and Distributed Deep Learning (DDL). the DDL models trained on a massive volume of data can outperform single accelerators being used, i.e., the performance of deep learning (DL) models can be enhanced by using distributed and parallel deep learning methods. But the DDL models need to be redesigned and evaluated for particular hardware resources and applications, requiring the literature on various DDL model evaluations for assistance. Authors in the proposed work design and evaluate DDL with data parallelism for classifying Diabetic retinopathy (DR) images. A performance comparative study on the DDL strategy implemented on DenseNet is presented where the model is trained on multi-GPUs with counts from 1 to 8. the results show that the model takes less time when trained on multi-GPUs compared to single GPU. the detailed evaluation analysis of DDL with data parallelism is presented in this paper. © 2023, the Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Graphics processing unit

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Re-structuring CNN using quantum layer executed on FPGA hardware for classifying 2-D data

Re-structuring CNN using quantum layer executed on FPGA hard...

引用

international conference on Integrated Circuits, Design, and Verification (ICDV)

作者： Nhat Hoang Bach Le Ha Vu Dinh Lam Tran thanh Toan Dao thi thu Hong Luu Duy Ninh Nguyen Institute of Electronics Academy of Science and Technology Hanoi Vietnam Electronic department University of Transport and Communications Hanoi Vietnam

ISBN: (数字)9798350371864

ISBN: (纸本)9798350371871

the article proposes a solution to restructure Convolutional Neural Network (CNN) architectures by integrating parameter quantization techniques with traditional CNN models capable of deployment on Field-Programmable Gate Array (FPGA) hardware for evaluating the classification performance of two-dimensional data in real-world scenarios. the solution introduces an additional quantum layer before the final classification layer of the CNN to receive standardized outputs, followed by computations in the Hilbert vector space to generate probability values for assessing classification results. the quantization process helps the model swiftly identify data features while optimizing the parallel computing capability of FPGA hardware. the model is evaluated on the MNIST handwritten digit dataset, revealing two advantages: time-processing on FPGA is four times faster compared to using only the Central processing Unit (CPU) on the PynQ-z2 kit board; classification accuracy is higher when utilizing the quantum layer compared to without it, with the same number of training iterations. these results demonstrate the feasibility of hardware-accelerated AI algorithms combined with quantum algorithms in real applications.

关键词： Quantization (signal) Computational modeling Hardware Data models Vectors Central processing Unit Convolutional neural networks

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Delay Margin Analysis of a Large-Scale Optimal Velocity Model using the parallel processing Delay Margin Finder (parDMF)

Delay Margin Analysis of a Large-Scale Optimal Velocity Mode...

引用

international conference on Control, Decision and Information Technologies (CoDIT)

作者： Duo Wang Adrián Ramírez Rifat Sipahi Northeastern University Boston MA USA Cátedras CONACYT México Division of Applied Mathematics IPICYT México

ISBN: (数字)9781728159539

ISBN: (纸本)9781728159546

A connected vehicle model with delays due to human reaction times and sensing and communication lines is considered. In particular, we investigate how time delays affect the equilibrium stability of this model in large scale. We focus mainly on the delay margin (DM) of this equilibrium, i.e., the largest delay that the system can accommodate without losing stability. We present how DM is influenced by the sparsity of sensor and communication lines and the number of vehicles. Different from previous work, no assumption is imposed on the structure of the network topology; the large-scale dynamics is treated in a computationally efficient manner by utilizing our recently developed parallel processing computational tool Delay Margin Finder (parDMF).

关键词： Delays Stability analysis Mathematical model Connected vehicles Vehicle dynamics Analytical models Microscopy

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Development and Application of a Monte Carlo Tree Search Algorithm for Simulating Da Vinci Code Game Strategies

Development and Application of a Monte Carlo Tree Search Alg...

引用

Intelligent Computing and Human-Computer Interaction (ICHCI), international conference on

作者： Ye Zhang Mengran Zhu Kailin Gui Jiayue Yu Yong Hao Haozhan Sun University of Pittsburgh Pittsburgh PA USA Miami University Oxford OH USA University of Washington Seattle WA USA Warner Bro. Discovery Culver City CA USA Columbia University New York NY USA Duke University Durham NC USA

ISBN: (数字)9798350368284

ISBN: (纸本)9798350368291

In this study, we explore the efficiency of the Monte Carlo Tree Search (MCTS), a prominent decision-making algorithm renowned for its effectiveness in complex decision environments, contingent upon the volume of simulations conducted. Notwithstanding its broad applicability, the algorithm's performance can be adversely impacted in certain scenarios, particularly within the domain of game strategy development. this research posits that the inherent branch divergence within the Da Vinci Code board game significantly impedes parallelism when executed on Graphics processing Units (GPUs). To investigate this hypothesis, we implemented and meticulously evaluated two variants of the MCTS algorithm, specifically designed to assess the impact of branch divergence on computational performance. Our comparative analysis reveals a linear improvement in performance with the CPU-based implementation, in stark contrast to the GPU implementation, which exhibits a non-linear enhancement pattern and discernible performance troughs. these findings contribute to a deeper understanding of the MCTS algorithm's behavior in divergent branch scenarios, highlighting critical considerations for optimizing game strategy algorithms on parallel computing architectures.

关键词： Solid modeling Monte Carlo methods Codes Computational modeling Instruction sets Graphics processing units Games parallel processing Time measurement Robots

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A parallel-Connected High Voltage Multiplier for Non-thermal Food processing

A Parallel-Connected High Voltage Multiplier for Non-Thermal...

引用

7th international conference on Electrical, Electronics and Civil Engineering(ICEECE’2015)

作者： Kei Eguchi Kanji Abe Shinya Terada Ichirou Oota the Department of Information Electronics Fukuoka Institute of Technology

In this paper, a parallel-connected high voltage multiplier is proposed for non-thermal food processing utilizing an underwater shockwave. the proposed multiplier consists of two positive multiplier blocks and two negative multiplier blocks. In the proposed multiplier, these multiplier blocks are operated in opposite polarity. By connecting these blocks in parallel, the proposed multiplier provides a high stepped-up voltage at high speed, where the output voltage across the output capacitor is generated by combining the outputs of these multiplier blocks. Concerning the proposed multiplier with six stages, simulation program with integrated circuit emphasis(SPICE) simulations and theoretical analysis using a four-terminal equivalent circuit are performed. the results of this study are as follows: 1) Settling time of the proposed voltage multiplier is less than 150 ms when the output capacitance is 10μF and 2) the theoretical results are in good agreement with SPICE simulated results. the derived theoretical equations are effective to estimate the power efficiency and output voltages of the proposed multiplier.

关键词： Cockcroft-Walton multipliers,High speed multipliers,Non-thermal food processing,parallel-connected multipliers

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High throughput FPGA implementation of Min-Sum LDPC Decoder Architecture for Wireless Communication Standards

High throughput FPGA implementation of Min-Sum LDPC Decoder ...

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Digital Signal processing and its Applications (DSPA), international conference on

作者： Pavel Nikishkin Ruslan Goriushkin Nikita Vinogradov Evgeny Likhobabin Vladimir Vityazev Ryazan State Radio Engineering University RSREU Ryazan Russia

this paper presents a min-sum decoder design for Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. the design is supported various LDPC Parity-Check matrices including the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.11n) standards matrices. New techniques such as pipelining of the decoding architecture core are proposed. these core calculate variable-to-check (VTC) and new check-to-variable (CTV) messages and also update estimate of posterior probabilities (APPs). the parallel multicore decoding architecture implies a prior shift of values based on the LDPC matrix and simultaneous calculation of values for the core. Proposed decoder is implemented on the Zynq-7000 Mini-ITX Evaluation Board (XC7Z100-2FFG900).

关键词： Multicore processing Signal processing algorithms WiMAX Probability throughput Parity check codes Decoding

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