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RNS Smith-Waterman Accelerator based on the moduli set 2n, 2n-1, 2n-1-1

RNS Smith-Waterman Accelerator based on the moduli set 2n, 2...

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international conference on Adaptive Science & Technology (ICAST)

作者： Patrick Kwabena Mensah Edem K. Bankas Mohammed Muniru Iddrisu Department of Computer Science University for Development Studies Navrongo Ghana Department of Mathematics University for Development Studies Navrongo Ghana

ISBN: (纸本)9781538642344

the Smith-Waterman algorithm is very sensitive but computationally intensive on general purpose CPUs. On the other hand, the FPGA has proven to be an excellent platform for accelerating the algorithm in addition to its low cost and power consumption. this paper therefore proposes the use of the parallelism and carry-free propagation properties of Residue Number Systems (RNS) to accelerate the algorithm on an FPGA; a deviation from the usual binary/decimal implementations. Compared to the only previous known work that uses RNS for this task, our implementation is (1) the first to employ the use of Linear Systolic Arrays (LSA), (2) avoid the use of Lookup Tables, (3) has a larger dynamic range and (4) aligns long sequences. Implemented on a modest hardware and on a Kintex7 FPGA, we achieved a performance improvement of 169 times over the general-purpose processor implementation. this result was obtained using the naïve implementation of LSAs, indicating the positive effects of using RNS.

关键词： Field programmable gate arrays Dynamic range Hardware DNA Acceleration parallel processing Clocks

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A low-cost fully pipelined architecture for fingerprint matching

A low-cost fully pipelined architecture for fingerprint matc...

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international conference on Signal processing Proceedings (ICSP)

作者： Jinwei Xu Jingfei Jiang Yong Dou Xiaolong Shen Science and Technology on Parallel and distributed Processing Laboratory National University of Defense Technology Changsha China

Fingerprint matching is a key procedure in fingerprint identification applications. the fingerprint-matching algorithm based on minutiae is one of the most typical algorithms that can achieve a reasonably correct recognition rate. Performance and cost are two critical factors when implementing minutia-based matching algorithms in most embedded applications. A low-cost, fully pipelined architecture for minutia-based fingerprint matching is proposed in this paper. A regular matching unit with a pipeline of 13 stages is designed as the core of the architecture, interfacing with a two-port RAM and a DDR3 controller. We implemented the whole architecture on a Xilinx FPGA board with the Virtex VII XC7VX485T chip. the matching unit can run with a frequency of 330 MHz on the chip, which leads the system to achieve a throughput of about 430000 fingerprints per second when processing typical datasets. the unit only occupies 568 slices, which is less than 1% of the available chip resources. the board only consumes 16 W of power when run. the architecture can gain about twice the throughput of the 2.93 GHz Intel Xeon5670 CPU at a low logic cost and power.

关键词： Fingerprint recognition throughput Random access memory Pipelines Computer architecture Field programmable gate arrays Algorithm design and analysis

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Counterfactual Gradients-based Quantification of Prediction Trust in Neural Networks

Counterfactual Gradients-based Quantification of Prediction ...

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IEEE conference on Multimedia Information processing and Retrieval (MIPR)

作者： Mohit Prabhushankar Ghassan AlRegib School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA

ISBN: (数字)9798350351422

ISBN: (纸本)9798350351439

the widespread adoption of deep neural networks in machine learning calls for an objective quantification of esoteric trust. In this paper we propose GradTrust, a classification trust measure for large-scale neural networks at inference. the proposed method utilizes variance of counterfactual gradients, i.e. the required changes in the network parameters if the label were different. We show that GradTrust is superior to existing techniques for detecting misprediction rates on 50000 images from ImageNet validation dataset. Depending on the network, GradTrust detects images where either the ground truth is incorrect or ambiguous, or the classes are co-occurring. We extend GradTrust to Video Action Recognition on Kinetics-400 dataset. We showcase results on 14 architectures pretrained on ImageNet and 5 architectures pretrained on Kinetics-400. We observe the following: (i) simple methodologies like negative log likelihood and margin classifiers outperform state-of-the-art uncertainty and out-of-distribution detection techniques for misprediction rates, and (ii) the proposed GradTrust is in the Top-2 performing methods on 37 of the considered 38 experimental modalities. the code is available at: https://***/olivesgatech/GradTrust

关键词： Uncertainty Codes Current measurement Measurement uncertainty Machine learning Information processing Artificial neural networks Reliability

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Adaptive load balancing Strategy for VR Microservices with Edge AI

Adaptive load balancing Strategy for VR Microservices with E...

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international conference on Electronics Technology (ICET)

作者： Liang Liu Yuxiang Chen Xun Shao Kailin Wang Yu Huang Zhongguancun Laboratory Beijing Beijing P.R.China University College London London United Kingdom Toyohashi University of Technology Toyohashi Japan Beijing University Of Posts and Telecommunications Beijing P.R.China

ISBN: (数字)9798350363951

ISBN: (纸本)9798350363968

the pervasiveness of information and communications technologies, such as 5 G and edge AI, has led to the booming growth of video applications, particularly in the realm of virtual reality (VR). However, due to the random distribution of the video traffic and the fluctuation of the computing power in Mobile Edge Computing (MEC) networks, traditional load balancing strategies lead to high video service response delay and low resource utilization. To this end, this paper designs and implements an adaptive dynamic load-balancing strategy for VR. Based on the performance monitoring function of the Kubernetes (k8s) system, we first utilize the reinforcement learning algorithm TD3 to find the optimal video service allocation at different edge nodes. then, considering the real-time GPU utilization of each edge computing node, the queue length, and the average transmission delay, we jointly optimize the average response delay of users and the work efficiency of nodes. Finally, we evaluate the proposed scheme on a real k8s system. Compared with traditional load balancing strategies, the proposed scheme reduces the latency by $16 \%$ to $52 \%$ and improves the work efficiency by $5 \%$ to $8 \%$.

关键词： Heuristic algorithms Microservice architectures Graphics processing units Edge AI Virtual reality Load management Real-time systems

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A fully digital Background calibration technique for pipeline analog-to-digital converters

A fully digital Background calibration technique for pipelin...

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international conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON

作者： Ziaeddin Koozeh Kanani Jafar Sobhi Mousa Yousefi Ahmad Tahmasebi Department of Electrical Engineering University of Tabriz Tabriz Iran Sarab Branch Islamic Azad University Sarab Iran

this paper describes a new background calibration technique for pipeline analog-to-digital converters (ADCs). the new scheme utilizes an existing digital foreground calibration algorithm and extends it to work in background. the goal is to digitally calibrate the pipeline ADCs in the background without stopping the input conversion. In this method one additional stage connected in parallel to the stage under calibration and one cyclic ADC are used to accommodate the calibration. the extra stage and the cyclic ADC are only used during the calibration process. Sources of error in pipeline architectures and effects of error on residue plot of 1-bit per stage are identified and discussed. the digital background calibration accounts for capacitor mismatch, comparator offset, charge injection and finite op-amp gain. By applying proposed calibration to a 12 bit resolution pipeline ADC, maximum INL improved from 14 to 0.6 LSB, and maximum DNL improved from 26 to 0.8 LSB.

关键词： Calibration Pipelines Analog-digital conversion Voltage Operational amplifiers Topology Signal processing algorithms Capacitors Signal resolution Aging

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Using the temporal logic programming language Tokio for algorithm description and automatic CMOS gate array synthesis 4th

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4th international conference on Logic Programming, 1985

作者： Fujita, Masahiro Ishisone, Makoto Nakamura, Hiroshi Tanaka, Hidehiko Moto-oka, Tohru Faculty of engineering University of Tokyo 7-3-1 Hongo Bunkyo_ku Tokyo113 Japan Fujitsu Laboratories Ltd. Japan

ISBN: (纸本)9783540164791

To date, simulation has been the primary method used to support hardware logic design. In particular, there has been little that could support such design from the system level, such as a language to describe processing algorithms. In this paper, we will propose a silicon compiler, which is designed to support CMOS gate arrays from the system level. Descriptions from the system level through the state diagram level are done by using the temporal logic programming language called Tokio. Being based on temporal logic, Tokio enables the use of temporal operators. this facilitates the description of concurrent operations that cannot be easily described in Prolog. In addition, because the mathematical models are clearly defined, verification and synthesis can be easily supported. At present, only a simulator coded in Prolog is available to support descriptions of this level in Tokio. A program that automatically synthesizes logical circuits for CMOS gate array from state diagram level is supported. the core of this program has already been developed in C-Prolog. Synthesis has already been tested at our laboratory. We used the Unify Processor (UP) of PIE (parallel Inference Machine) which is currently under development, as an example. this paper introduces the hardware design support strategy based on Tokio, and explains the details of the program that synthesizes CMOS gate arrays from the descriptions of the state diagram level. © 1986, Springer-Verlag.

关键词： Computer circuits

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Spreadsheet model for MorphoSys RC array

Spreadsheet model for MorphoSys RC array

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： H. Diab E. Abdennour N. Mansour Department of Electrical and Computer Eng'g Faculty of Engineering and Architecture American University of Beirut Beirut Lebanon Computer Science Program Lebanese American University Beirut Lebanon

ISBN: (纸本)0780365429

this paper introduces reconfigurable computing and MorphoSys, which is a reconfigurable system. It also explains the architecture of its reconfigurable hardware part. then, it presents two spreadsheet models for the operation of this reconfigurable device. the first spreadsheet performs the modelling through formulas, while the second does it numerically. these spreadsheet models serve as design and debugging tools.

关键词： Registers Hardware Computer architecture Application software Reduced instruction set computing Multiplexing Numerical models Debugging Application specific integrated circuits parallel processing

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MPSoC architecture for H.264/AVC intra prediction chain on SoCLiB platform and FPGA technology

MPSoC architecture for H.264/AVC intra prediction chain on S...

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international conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)

作者： N. Belhadj M. Turki Z. Marrakchi M. Ali Ben Ayed N. Masmoudi H. Mehrez Laboratory of Electronics and Technology of Information from the National Engineering University of Sfax Tunisia Laboratory of Computer Sciences LIP6 University of Pierre and Marie Curie Paris France

Multiprocessor System on Chip (MPSoC) technology can present an interesting solution to reduce the computational time of complex applications. Execute the H.264/AVC encoder on MPSoC architecture, is becoming an interesting point of research that can mitigate its algorithmic complexity and to resolve the real time constraints. In this paper, we present an efficient MPSoC architecture for the intra prediction process which is an important module of the H.264/AVC video encoder, using Data Level parallelism (DLP) partitioning. this architecture is tested on an open platform for MPSoC architectures virtual designing (SoCLiB), and validated on FPGA technology. Experimental results show a gain of 74% in term of encoding speed when using four processors for coding a High Definition Video sequence (HDV) compared to uni-processor architecture.

关键词： Computer architecture Program processors Video coding Encoding Field programmable gate arrays parallel processing Partitioning algorithms

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A parallel Retinex Image Enhancement Algorithm Based on OpenMP 16th

A Parallel Retinex Image Enhancement Algorithm Based on Open...

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16th IFIP WG 10.3 international conference on Network and parallel Computing, NPC 2019

作者： Cheng, Shixiong Liu, Bin He, Dongjian He, Jinrong Li, Yuancheng Du, Yanning College of Information Engineering Northwest A&F University YanglingShaanxi China Key Laboratory of Agricultural Internet of Things Northwest A&F University Ministry of Agriculture and Rural Affairs YanglingShaanxi712100 China Shaanxi Key Laboratory of Agricultural Information Perception and Intelligent Service Northwest A&F University YanglingShaanxi712100 China College of Mechanical and Electronic Engineering Northwest A&F University YanglingShaanxi China College of Mathematics and Computer Science Yan’an University Yan’an Shaanxi China School of Computer Science and Technology Xi’an University of Science and Technology Xi’an China School of Computer Science and Engineering Xi’an University of Technology Xi’an China

ISBN: (纸本)9783030307080

Retinex image enhancement algorithm occupies an important position in eliminating image uneven exposure, low contrast, and smog influence. However, with the increasing of image resolution, the real-time performance of the serial Retinex algorithm has not satisfied the requirements of practical applications. this paper proposes an OpenMP-based parallel Retinex algorithm. the parallelism of the Retinex algorithm is first identified by theoretical analyses. then, the time-consuming sub-algorithms such as Gaussian convolution and exponential transformation, of the serial algorithm are designed and executed in parallel. On Tianhe-2 supercomputer platform, the experimental results show that the speedup of the parallel algorithm is significantly improved, and the test image set achieves an average speedup of 12. It indicates that the parallel algorithm can satisfy the needs of real-time processing in image enhancement field. © 2019, IFIP international Federation for Information processing.

关键词： Image enhancement

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Language Comparison via Network Topology 1

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7th international conference on Statistical Language and Speech processing, SLSP 2019

作者： Škrlj, Blaž Pollak, Senja Jožef Stefan International Postgraduate School Ljubljana Slovenia Jožef Stefan Institute Ljubljana Slovenia Usher Institute Medical School University of Edinburgh Edinburgh United Kingdom

ISBN: (数字)9783030313722

ISBN: (纸本)9783030313715

Modeling relations between languages can offer understanding of language characteristics and uncover similarities and differences between languages. Automated methods applied to large textual corpora can be seen as opportunities for novel statistical studies of language development over time, as well as for improving cross-lingual natural language processing techniques. In this work, we first propose how to represent textual data as a directed, weighted network by the text2net algorithm. We next explore how various fast, network-topological metrics, such as network community structure, can be used for cross-lingual comparisons. In our experiments, we employ eight different network topology metrics, and empirically showcase on a parallel corpus, how the methods can be used for modeling the relations between nine selected languages. We demonstrate that the proposed method scales to large corpora consisting of hundreds of thousands of aligned sentences on an of-the-shelf laptop. We observe that on the one hand properties such as communities, capture some of the known differences between the languages, while others can be seen as novel opportunities for linguistic studies. © 2019, Springer Nature Switzerland AG.

关键词： Network topology

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