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检索条件"任意字段=7th International Conference on Algorithms and Architectures for Parallel Processing"
2981 条 记 录,以下是2871-2880 订阅
the data-parallel categorical abstract machine  5th
The data-parallel categorical abstract machine
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5th international conference on parallel architectures and Languages Europe, PARLE 1993
作者: Hains, Gaétan Foisy, Christian Département d’Informatique et Recherche Opérationnelle Université de Montréal MontréalQCH3C 3J7 Canada
Data-parallel ML is proposed for compilation to a distributed version (DPCAM) of Cousineau, Curien and Mauny’s Categorical Abstract Machine. the DPCAM is a static network of CAMs which dynamically restrict the MIMD e... 详细信息
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Dynamic switching of coherent cache protocols and its effects on doacross loops  93
Dynamic switching of coherent cache protocols and its effect...
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7th international conference on Supercomputing, ICS 1993
作者: Matsumoto, Takashi Hiraki, Kei Department of Information Science University of Tokyo 7-3-1 Hongo Bunkyo-ku Tokyo113 Japan
In multiprocessor systems, overheads caused by inter-processor communication and synchronization have been one of the largest obstacles for efficient execution of parallel programs. To reduce these overheads in shared... 详细信息
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Independent performance modeling of parallel architectures and algorithms
Independent performance modeling of parallel architectures a...
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international conference on Computing and Information (ICCI)
作者: E.E. Johnson Parallel Architecture Research Laboratories New Mexico State University USA
A key requirement for the effective use of multiprocessor systems in real-world applications is an ability to accurately predict the performance of a specific algorithm on a specific architecture. Such performance pre... 详细信息
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Connectionist modeling and parallel architectures  93
Connectionist modeling and parallel architectures
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Proceedings of the 7th international conference on Neural Information processing Systems
作者: Joachim Diederich Ah Chung Tsoi Neurocomputing Research Centre School of Computing Science Queensland University of Technology Brisbane Australia Department of Electrical and Computer Engineering University of Queensland St Lucia Queensland Australia
the introduction of specialized hardware platforms for connectionist modeling ("connectionist supercomputer") has created a number of research topics. Some of these issues are controversial, e.g. the efficie...
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A massively-parallel SIMD processor for neural network and machine vision applications  93
A massively-parallel SIMD processor for neural network and m...
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Proceedings of the 7th international conference on Neural Information processing Systems
作者: Michael A. Glover W. thomas Miller, III Current Technology Inc. Durham NH Department of Electrical and Computer Engineering The University of New Hampshire Durham NH
this paper describes the MM32k, a massively-parallel SIMD computer which is easy to program, high in performance, low in cost and effective for implementing highly parallel neural network architectures. the MM32k has ...
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A scalar architecture for pseudo vector processing based on slide-windowed registers  93
A scalar architecture for pseudo vector processing based on ...
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7th international conference on Supercomputing, ICS 1993
作者: Nakamura, Hiroshi Boku, Taisuke Wada, Hideo Imori, Hiromitsu Nakata, Ikuo Inagami, Yasuhiro Nakazawa, Kisaburo Yamashtta, Yoshiyuki Institute of Information Sciences and Electronics University of Tsukuba Tsukuba Ibaraki305 Japan General Purpose Computer Division Hitachi Ltd. Hadano Kanagawa259-13 Japan Central Research Laboratory Hitachi Ltd. Kokubunji Tokyo185 Japan
In this paper, we present a new scalar architecture for high-speed vector processing. Without using cache memory, the proposed architecture tolerates main memory access latency by introducing slide-windowed floating-p... 详细信息
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Incomplete Star Graph : An Economical Fault-tolerant Interconnection Network
Incomplete Star Graph : An Economical Fault-tolerant Interco...
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international conference on parallel processing (ICPP)
作者: CP. Ravikumar A. Kuchlous G. Manimaran Electrical Engineering Department Indian Institute of Technology New Delhi India National Informatics Centre (NIC) New Delhi India
A number of existing multiprocessors are based on the hypercube interconnection network. the popularity of the hypercube is due to its small communication diameter, which grows logarithmically with the cube size, its ... 详细信息
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Distributed modeling and implementation of high performance communication architectures
Distributed modeling and implementation of high performance ...
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international conference on Distributed Computing Systems
作者: K. Shafer M. Ahuja Office of Research Online Computer Library Center Inc. Dublin OH USA Department of Comp. Science and Engineering University of California San Diego CA USA
High performance distributed computing systems require high performance communication systems. Distributed modeling and implementation of these communication systems is important. Toward this goal, the authors refine ... 详细信息
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Efficient simulation of biological neural networks on massively parallel supercomputers with hypercube architecture  93
Efficient simulation of biological neural networks on massiv...
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Proceedings of the 7th international conference on Neural Information processing Systems
作者: Ernst Niebur Dean Brettle Computation and Neural Systems California Institute of Technology Pasadena CA Booz Allen and Hamilton Inc. McLean VA
We present a neural network simulation which we implemented on the massively parallel Connection Machine 2. In contrast to previous work, this simulator is based on biologically realistic neurons with nontrivial singl...
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VLSI phase locking architectures for feature linking in multiple target tracking systems  93
VLSI phase locking architectures for feature linking in mult...
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Proceedings of the 7th international conference on Neural Information processing Systems
作者: Andreas G. Andreou thomas G. Edwards Department of Electrical and Computer Engineering The Johns Hopkins University Baltimore MD Department of Electrical Engineering The University of Maryland College Park MD
Recent physiological research has shown that synchronization of oscillatory responses in striate cortex may code for relationships between visual features of objects. A VLSI circuit has been designed to provide rapid ...
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