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Deep Learning-based Text-in-Image Watermarking

Deep Learning-based Text-in-Image Watermarking

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IEEE conference on Multimedia Information processing and Retrieval (MIPR)

作者： Bishwa Karki Chun-Hua Tsai Pei-Chi Huang Xin Zhong Department of Computer Science University of Nebraska Omaha Omaha NE USA Information Systems and Quantitative Analysis University of Nebraska Omaha Omaha NE USA

ISBN: (数字)9798350351422

ISBN: (纸本)9798350351439

In this work, we introduce a novel deep learning- based approach to text-in-image watermarking, a method that embeds and extracts textual information within images to en-hance data security and integrity. Leveraging the capabilities of deep learning, specifically through the use of Transformer- based architectures for text processing and Vision Transformers for image feature extraction, our method sets new benchmarks in the domain. the proposed method represents the first application of deep learning in text-in-image watermarking that improves adaptivity, allowing the model to intelligently adjust to specific image characteristics and emerging threats. through testing and evaluation, our method has demonstrated superior robustness compared to traditional watermarking techniques, achieving enhanced imperceptibility that ensures the watermark remains undetectable across various image contents.

关键词： Deep learning Computer vision Data security Watermarking Information processing Transformers Feature extraction Robustness Data mining Text processing

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Simulation of a Dubai based 200 KW power plant using PVsyst Software

Simulation of a Dubai based 200 KW power plant using PVsyst ...

引用

international conference on Signal processing and Integrated Networks (SPIN)

作者： Malvika Satish Sharon Santhosh Apurv Yadav Solar and Alternater Energy Amity University Dubai Dubai United Arab Emirates

ISBN: (数字)9781728154756

ISBN: (纸本)9781728154763

With the exhaustion of fossil fuels, their dreadful effect on the environment and their soaring prices, renewable forms of energy like solar and wind power have emerged rapidly, as clean and sustainable sources of generating electricity. this paper studies the viability of deploying a 200 kWp on-grid monocrystalline silicon solar plant, by making use of PVsyst software for Dubai international academic city, Dubai. the system was designed to have 22 modules in series with 32 strings in parallel. And the total number of modules is computed as 704. the reports of the simulation were examined to determine the total production of energy and specific energy production which was found to be 352.6 MWh/year and 1757 kWh/kWp/year respectively. the annual performance ratio of the system was calculated as 81.67 %. Lastly, by identifying the main source of losses, the detailed loss for the entire year is estimated and represented by an arrow loss diagram.

关键词： Software Photovoltaic systems Production Inverters Tools Signal processing

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Designing A Unified Architecture Graphics processing Unit

Designing A Unified Architecture Graphics Processing Unit

引用

CENet 2017-the 7th international conference on Computer Engineering and Networks

作者： Lingjuan Wu Liang Huang Tinggang Xiong Wuhan Digital Engineering Institute

Graphics processing Unit(GPU) performs graphics computing and its architecture has developed from the fixed function pipeline to the programmable unified *** architecture promises dynamic load balancing and guarantees the high parallel computing of *** paper presents the design and implementation of a unified architecture *** unified shader is based on the SIMD and SIMT *** the thread level,SIMT guarantees the full-load capability of unified shader by thread managing and *** the instruction level,SIMD controls the execution of the unified shader hardware *** finish the algorithm,architecture design and Verilog RTL *** verification results on FPGA show that the proposed GPU works correctly and its vertex and fragment processing speed reaches one unit per clock cycle.

关键词： GPU Designing A Unified Architecture Graphics processing Unit processing

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RNS Smith-Waterman Accelerator based on the moduli set 2n, 2n-1, 2n-1-1

RNS Smith-Waterman Accelerator based on the moduli set 2n, 2...

引用

international conference on Adaptive Science & Technology (ICAST)

作者： Patrick Kwabena Mensah Edem K. Bankas Mohammed Muniru Iddrisu Department of Computer Science University for Development Studies Navrongo Ghana Department of Mathematics University for Development Studies Navrongo Ghana

ISBN: (纸本)9781538642344

the Smith-Waterman algorithm is very sensitive but computationally intensive on general purpose CPUs. On the other hand, the FPGA has proven to be an excellent platform for accelerating the algorithm in addition to its low cost and power consumption. this paper therefore proposes the use of the parallelism and carry-free propagation properties of Residue Number Systems (RNS) to accelerate the algorithm on an FPGA; a deviation from the usual binary/decimal implementations. Compared to the only previous known work that uses RNS for this task, our implementation is (1) the first to employ the use of Linear Systolic Arrays (LSA), (2) avoid the use of Lookup Tables, (3) has a larger dynamic range and (4) aligns long sequences. Implemented on a modest hardware and on a Kintex7 FPGA, we achieved a performance improvement of 169 times over the general-purpose processor implementation. this result was obtained using the naïve implementation of LSAs, indicating the positive effects of using RNS.

关键词： Field programmable gate arrays Dynamic range Hardware DNA Acceleration parallel processing Clocks

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Adaptive load balancing Strategy for VR Microservices with Edge AI

Adaptive load balancing Strategy for VR Microservices with E...

引用

international conference on Electronics Technology (ICET)

作者： Liang Liu Yuxiang Chen Xun Shao Kailin Wang Yu Huang Zhongguancun Laboratory Beijing Beijing P.R.China University College London London United Kingdom Toyohashi University of Technology Toyohashi Japan Beijing University Of Posts and Telecommunications Beijing P.R.China

ISBN: (数字)9798350363951

ISBN: (纸本)9798350363968

the pervasiveness of information and communications technologies, such as 5 G and edge AI, has led to the booming growth of video applications, particularly in the realm of virtual reality (VR). However, due to the random distribution of the video traffic and the fluctuation of the computing power in Mobile Edge Computing (MEC) networks, traditional load balancing strategies lead to high video service response delay and low resource utilization. To this end, this paper designs and implements an adaptive dynamic load-balancing strategy for VR. Based on the performance monitoring function of the Kubernetes (k8s) system, we first utilize the reinforcement learning algorithm TD3 to find the optimal video service allocation at different edge nodes. then, considering the real-time GPU utilization of each edge computing node, the queue length, and the average transmission delay, we jointly optimize the average response delay of users and the work efficiency of nodes. Finally, we evaluate the proposed scheme on a real k8s system. Compared with traditional load balancing strategies, the proposed scheme reduces the latency by $16 \%$ to $52 \%$ and improves the work efficiency by $5 \%$ to $8 \%$.

关键词： Heuristic algorithms Microservice architectures Graphics processing units Edge AI Virtual reality Load management Real-time systems

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Using the temporal logic programming language Tokio for algorithm description and automatic CMOS gate array synthesis 4th

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4th international conference on Logic Programming, 1985

作者： Fujita, Masahiro Ishisone, Makoto Nakamura, Hiroshi Tanaka, Hidehiko Moto-oka, Tohru Faculty of engineering University of Tokyo 7-3-1 Hongo Bunkyo_ku Tokyo113 Japan Fujitsu Laboratories Ltd. Japan

ISBN: (纸本)9783540164791

To date, simulation has been the primary method used to support hardware logic design. In particular, there has been little that could support such design from the system level, such as a language to describe processing algorithms. In this paper, we will propose a silicon compiler, which is designed to support CMOS gate arrays from the system level. Descriptions from the system level through the state diagram level are done by using the temporal logic programming language called Tokio. Being based on temporal logic, Tokio enables the use of temporal operators. this facilitates the description of concurrent operations that cannot be easily described in Prolog. In addition, because the mathematical models are clearly defined, verification and synthesis can be easily supported. At present, only a simulator coded in Prolog is available to support descriptions of this level in Tokio. A program that automatically synthesizes logical circuits for CMOS gate array from state diagram level is supported. the core of this program has already been developed in C-Prolog. Synthesis has already been tested at our laboratory. We used the Unify Processor (UP) of PIE (parallel Inference Machine) which is currently under development, as an example. this paper introduces the hardware design support strategy based on Tokio, and explains the details of the program that synthesizes CMOS gate arrays from the descriptions of the state diagram level. © 1986, Springer-Verlag.

关键词： Computer circuits

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MPSoC architecture for H.264/AVC intra prediction chain on SoCLiB platform and FPGA technology

MPSoC architecture for H.264/AVC intra prediction chain on S...

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international conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)

作者： N. Belhadj M. Turki Z. Marrakchi M. Ali Ben Ayed N. Masmoudi H. Mehrez Laboratory of Electronics and Technology of Information from the National Engineering University of Sfax Tunisia Laboratory of Computer Sciences LIP6 University of Pierre and Marie Curie Paris France

Multiprocessor System on Chip (MPSoC) technology can present an interesting solution to reduce the computational time of complex applications. Execute the H.264/AVC encoder on MPSoC architecture, is becoming an interesting point of research that can mitigate its algorithmic complexity and to resolve the real time constraints. In this paper, we present an efficient MPSoC architecture for the intra prediction process which is an important module of the H.264/AVC video encoder, using Data Level parallelism (DLP) partitioning. this architecture is tested on an open platform for MPSoC architectures virtual designing (SoCLiB), and validated on FPGA technology. Experimental results show a gain of 74% in term of encoding speed when using four processors for coding a High Definition Video sequence (HDV) compared to uni-processor architecture.

关键词： Computer architecture Program processors Video coding Encoding Field programmable gate arrays parallel processing Partitioning algorithms

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Real-time implementation of stereo vision based on optimised normalised cross-correlation and propagated search range on a GPU

Real-time implementation of stereo vision based on optimised...

引用

IEEE international Workshop on Imaging Systems and Techniques (IST)

作者： Rui Fan Naim Dahnoun Visual Information Laboratory University of Bristol UK Department of Electrical and Electronic Engineering University of Bristol UK

Due to the trade-offs between accuracy and speed, binocular stereo vision is still a challenging task in 3D computer vision research area. In this paper, an efficient stereo matching algorithm is implemented on a state-of-the-art GPU to achieve highly accurate disparity maps in real time for various autonomous vehicle applications. the proposed algorithm is developed from our previous paper, where the search range at row v is propagated from three estimated neighbourhood disparities located at row v + 1. In order to speed up the execution, the prevalent NCC algorithm is optimised by factorising the equation into five independent parts. the computations of hi, H r , aj and a r are accelerated by using the integral images II, Ir, 12 and I r 2. the values of h and a are stored in static program storage for indexing during the stereo matching, which further reduces expensive calculations to help the system perform in real time. the main purpose of this work is to accelerate the processing speed by highly exploiting the parallel computing architectures (OpenMP and CUDA). the performance of the implementation on an NVIDIA GTX 970M GPU is compared with the performance of the implementations on an Intel Core i7-4720HQ CPU using both single thread and multiple threads. the experimental results illustrate that the GPU implementation yields 37 fps when processing the images (resolution: 1242 × 375) from the KITTI database, which is between two and nine times faster than the implementations on the CPU using a different number of threads.

关键词： Graphics processing units Mathematical model Acceleration Real-time systems parallel processing Heuristic algorithms Estimation

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A parallel Retinex Image Enhancement Algorithm Based on OpenMP 16th

A Parallel Retinex Image Enhancement Algorithm Based on Open...

引用

16th IFIP WG 10.3 international conference on Network and parallel Computing, NPC 2019

作者： Cheng, Shixiong Liu, Bin He, Dongjian He, Jinrong Li, Yuancheng Du, Yanning College of Information Engineering Northwest A&F University YanglingShaanxi China Key Laboratory of Agricultural Internet of Things Northwest A&F University Ministry of Agriculture and Rural Affairs YanglingShaanxi712100 China Shaanxi Key Laboratory of Agricultural Information Perception and Intelligent Service Northwest A&F University YanglingShaanxi712100 China College of Mechanical and Electronic Engineering Northwest A&F University YanglingShaanxi China College of Mathematics and Computer Science Yan’an University Yan’an Shaanxi China School of Computer Science and Technology Xi’an University of Science and Technology Xi’an China School of Computer Science and Engineering Xi’an University of Technology Xi’an China

ISBN: (纸本)9783030307080

Retinex image enhancement algorithm occupies an important position in eliminating image uneven exposure, low contrast, and smog influence. However, with the increasing of image resolution, the real-time performance of the serial Retinex algorithm has not satisfied the requirements of practical applications. this paper proposes an OpenMP-based parallel Retinex algorithm. the parallelism of the Retinex algorithm is first identified by theoretical analyses. then, the time-consuming sub-algorithms such as Gaussian convolution and exponential transformation, of the serial algorithm are designed and executed in parallel. On Tianhe-2 supercomputer platform, the experimental results show that the speedup of the parallel algorithm is significantly improved, and the test image set achieves an average speedup of 12. It indicates that the parallel algorithm can satisfy the needs of real-time processing in image enhancement field. © 2019, IFIP international Federation for Information processing.

关键词： Image enhancement

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Performance evaluation of Distributed Arithmetic based MAC Structures for DSP Applications

Performance evaluation of Distributed Arithmetic based MAC S...

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international conference on Smart Structures and Systems (ICSSS)

作者： M. Bharathi Yasha Jyothi M Shirur P.L. Lahari Sree Vidyanikethan Engineering College Tirupathi BNM institute of Technology Banglore

ISBN: (数字)9781728172231

ISBN: (纸本)9781728172286

MAC is an essential core which is used in every Digital signal processor. the primary focal point of this article is to introduce a high performance Distributed based (DA) MAC and offset binary coding Distributed Arithmetic (DA) based MAC for real time Signal processing Applications. Addition and multiplication are the two hardware resources widely used to design any arithmetic blocks in many fields like video processing, audio processing, speech processing and medical image processing applications. In this article, a literature survey is done on different MAC [2] units with different multipliers to generate partial products and to perform accumulation. Developed a DA based and offset binary coding DA based MAC cores which offers greater speed compared with different conventional MAC's using various multipliers. the coding for DA and offset based architectures are done using Verilog and simulation, synthesis are performed in Xilinx 14.7 Integrated Simulation Environment version. It achieves best area and less delay result when compared with previous approximate adder designs. the results of DA based MAC cores gives much more efficient in delay whereas offset binary coding-based DA offers both speed and area optimization.

关键词： Delays Table lookup Adders conferences Encoding Intelligent structures Digital signal processing

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