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检索条件"任意字段=7th International Conference on Algorithms and Architectures for Parallel Processing"

共 2976 条记录，以下是281-290 订阅

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18th international conference on algorithms and architectures for parallel processing, ICA3PP 2018

18th International Conference on Algorithms and Architecture...

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18th international conference on algorithms and architectures for parallel processing - ICA3PP 2018 Collocated Workshops: ICA3PP 2018 Workshop on Intelligent algorithms for Large-scale Complex Optimization Problems, IALCOP 2018, ICA3PP 2018 Workshop on Security and Privacy in Data processing, SPDP 2018

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Design of a Tourism Area Dining Recommendation System Based on Autoabstract Technology

Design of a Tourism Area Dining Recommendation System Based ...

引用

Computer Information Science and Application Technology (CISAT), international conference on

作者： Jilin Qin Joey S. Aviles Graduate School Angeles University Foundation Angeles City Philippines

ISBN: (数字)9798350375107

ISBN: (纸本)9798350375114

this study aims to address the issue of tourists choosing suitable restaurants and food in tourist areas, and proposes a tourist area dining recommendation system based on automatic summarization technology. the system utilizes web content scraping robots, a topic-aware Transformer model, and automatic summarization technology to automatically obtain introductions and summary comments for various restaurants in tourist areas, and to provide automatic dining recommendations. the research also combines Hadoop platform technology to establish parallel processing for real-time provision of food reviews and recommendation services. the innovation of this study lies in the use of automatic summarization technology and parallel processing to achieve rapid acquisition and recommendation of food information in tourist areas, providing convenient and practical services for tourists. this system has certain application prospects and promotional value in the field of tourist area dining recommendations.

关键词： Technological innovation Information science Reviews Computational modeling Text summarization parallel processing Transformers Real-time systems Recommender systems Robots

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Scheduling Algorithm for Low Energy Consumable parallel Task Application Based on DVFS 1

引用

7th international conference on Smart Computing and Communication, SmartCom 2022

作者： Liu, Xun Zhao, Hui College of Computer Science and Technology Wuhan University of Science and Technology Hubei Province Key Laboratory of Intelligent Information Processing and Real-Time Industrial System Wuhan China Henan University Kaifeng475000 China

ISBN: (数字)9783031281242

ISBN: (纸本)9783031281235

With the continuous improvement of various high-performance computing systems, various data centers had also been fully expanded. Energy consumption and actual performance measurement were very important indicators, which were also key issues in how to judge parallel calls for some tasks in high-performance computer systems. Modern processors were basically equipped with software control functions such as DVFS (Dynamic Voltage Frequency Scaling), in the actual system operation to ensure that the system could ensure the reasonable operation of the system while reducing energy consumption indicators. this paper considered how the designed scheduling algorithm first divides tasks reasonably to ensure that the maximum completion time and energy consumption of the processor were sufficiently reduced when the directed acyclic graph was executed. then considered making reasonable adjustments to the processor frequency using DVFS technology to adapt to the task while ensuring the critical path of the task. At the end of the article, make sure that the experimental verification algorithm could ensure that the task was completed and could reduce the energy consumption during task execution as much as possible. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Energy utilization

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Automatic Mapping of parallel Pattern-Based algorithms on Heterogeneous architectures 34th

Automatic Mapping of Parallel Pattern-Based Algorithms on He...

引用

34th international conference on Architecture of Computing Systems (ARCS)

作者： Truemper, Lukas Miller, Julian Terboven, Christian Mueller, Matthias S. Huddly AS Oslo Norway Rhein Westfal TH Aachen IT Ctr Chair High Performance Comp Aachen Germany

ISBN: (纸本)9783030816827;9783030816810

Nowadays, specialized hardware is often found in clusters to improve compute performance and energy efficiency. the porting and tuning of scientific codes to these heterogeneous clusters requires significant development efforts. To mitigate these efforts while maintaining high performance, modern parallel programming models introduce a second layer of abstraction, where an architecture-agnostic source code can be maintained and automatically optimized for the target architecture. However, with increasing heterogeneity, the mapping of an application to a specific architecture itself becomes a complex decision requiring a differentiated consideration of processor features and algorithmic properties. Furthermore, architecture-agnostic global transformations are necessary to maximize the simultaneous utilization of different processors. therefore, we introduce a combinatorial optimization approach to globally transform and automatically map parallel algorithms to heterogeneous architectures. We derive a global transformation and mapping algorithm which bases on a static performance model. Moreover, we demonstrate the approach on five typical algorithmic kernels showing automatic and global transformations such as loop fusion, re-ordering, pipelining, NUMA awareness, and optimal mapping strategies to an exemplary CPU-GPU compute node. Our algorithm achieves performance on par with hand-tuned implementations of all five kernels.

关键词： Mapping Heterogeneous architectures Global transformations parallel patterns Performance portability

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Fast Spectral Clustering Based on Fusion Density Peaks

Fast Spectral Clustering Based on Fusion Density Peaks

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international conference on Big Data and Artificial Intelligence (BDAI)

作者： Yi Gao Rong Luo Wu Yang School of Computing and Artificial Intelligence Southwest Jiaotong University Chengdu China School of Mathematics Southwest Jiaotong University Chengdu China School of Information Science and Technology Southwest Jiaotong University Chengdu China

ISBN: (数字)9798350352009

ISBN: (纸本)9798350352016

In recent years, Spectral Clustering and its variants have attracted much attention due to their excellent clustering performance. these algorithms first build a graph on the data based on local similarity, then compute the spectral decomposition of the Laplacian matrix of the graph, and finally achieve clustering by performing K-Means on embeddings obtained from spectral decomposition. However, the traditional spectral clustering method is difficult to deal with large-scale datasets. the large size of data will make the spectral decomposition slow and consume a lot of computational resources. To solve these problem, this paper first proposes a clustering algorithm named FGDPSC. FGDP-SC identifies global density peak points of the data as anchors in multi-scales defined by near-field, mid-field, and farfield, characterizes the data using a bipartite graph with anchors, and performs clustering efficiently through the transfer-cut of the bipartite graph. Experiments on real-world data validate the effectiveness of the proposed algorithms, especially on largescale data, by outperforming the classical Spectral Clustering algorithm and its main variants.

关键词： Accuracy Laplace equations Data analysis Clustering methods Buildings Clustering algorithms parallel processing Big Data Bipartite graph Matrix decomposition

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Optimized FPGA architectures for High-Speed NTT Computation

Optimized FPGA Architectures for High-Speed NTT Computation

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Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), international conference on

作者： Chetan Harsha Lekkala Sitadevi Bharatula B. Naresh Kumar Reddy K Sarangam Department of ECE Amrita School of Engineering Chennai India

ISBN: (数字)9798350356236

ISBN: (纸本)9798350356243

this research paper aims to enhance the performance of Number theoretic Transform (NTT) operations in cryptographic applications by leveraging the flexibility and parallel processing capabilities of Field Programmable Gate Arrays (FPGAs). NTT, integral to many cryptographic algorithms, often faces real-time performance challenges due to computational demands. By implementing NTT on FPGAs, this approach introduces features such as parallelism, pipelining, and dynamic memory management, significantly improving computational efficiency. the proposed architecture, utilizing 8T SRAM on the AMD Kintex 7 FPGA KC705 Kit, optimizes memory bandwidth and polynomial multiplication, resulting in a robust, high-speed implementation suitable for real-time cryptographic tasks. Simu-lation results demonstrate substantial performance gains, offering a valuable framework for future cryptographic hardware designs.

关键词： Random access memory Transforms Logic gates Hardware Real-time systems Stability analysis Computational efficiency Cryptography Field programmable gate arrays Pipeline processing

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A parallel PCA-SIFT Algorithm Based on Raspberry Pi 4B 23

A Parallel PCA-SIFT Algorithm Based on Raspberry Pi 4B

引用

Proceedings of the 2023 7th international conference on Electronic Information Technology and Computer Engineering

作者： Wei Wang Wang Li Zongliang Zhang College of Computer Engineering Jimei University China

ISBN: (纸本)9798400708305

Aiming at the problems of limited computing power of embedded platform, low target detection probability and high false alarm rate in the process of video small target tracking, a parallel PCA-SIFT algorithm based on Raspberry Pi 4B microprocessor is proposed. the data-level parallel method is used to realize parallel feature extraction and feature point matching, and the computing tasks are assigned to each CPU for parallel processing to improve the efficiency of the algorithm. the experimental results show that the algorithm has good adaptability to factors such as target and background clutter, geometric deformation, noise interference and illumination influence, and is close to the serial PCA-SIFT algorithm in image matching effect.

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A High-Speed Multiplier Design Using 2—Bit Reordering 4:3 Counter in a Wallace Tree Structure

A High-Speed Multiplier Design Using 2—Bit Reordering 4:3 C...

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international conference on Trends in Electronics and Informatics (ICEI)

作者： Saleem Syed Abdul Khader Khaderabad Sahithi Ankirapalli Swathi Lingamgunta Sasi Priyanka thammisetty Jaffar Ali Syed Dept. of Electronics and Communication Engineering Annamacharya Institute of Technology and Sciences Kadapa India

ISBN: (数字)9798331544607

ISBN: (纸本)9798331544614

It is known that the multiplier is widely applied, and to produce the outputs for the next stage, there is a reliance on the previous stage. Due to this, the multiplication process takes time to complete. As the binary bit counts of the multiplier and multiplicand increase, it takes longer to generate the output. this longer delay can severely impair the overall performance of digital systems, especially in applications requiring high-speed computations. therefore, optimizing the Multiplier for both speed and power efficiency is crucial to enhancing the performance of modern computing architectures. To achieve this optimization, various techniques such as parallel processing and reduced gate counts can be employed. Moreover, utilising advanced algorithms and hardware accelerators can enhance the efficiency of these multipliers in challenging computational settings. this will affect the circuit performance. A new technique known as the reordering technique is implemented in this project to enhance the multiplier in terms of speed and efficiency. this method is implemented by separating the high-state bits from the low-state bits using the reordering circuit, and then the separated bits are processed in the usual manner. this helps in the reduction of critical path latency, which benefits by enhancing the circuit's power consumption as less power is being released as heat or another form.

关键词： Micromechanical devices Power demand Logic gates parallel processing Market research Delays Table lookup Informatics Adders Optimization

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Designing a Deep Neural Network Model for Finding Semantic Similarity between Short Persian Texts Using a parallel Corpus 7

Designing a Deep Neural Network Model for Finding Semantic S...

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7th international conference on Web Research, ICWR 2021

作者： Sadat Hosseini Moghadam Emami, Zahra Tabatabayiseifi, Shohreh Izadi, Mohammad Tavakoli, Mohammad Science and Culture University Computer Engineering Tehran Iran Sharif University of Technology Artificial Intelligence Tehran Iran Sharif University of Technology Computer Engineering Tehran Iran Sharif University of Technology Computational Linguistics Tehran Iran

ISBN: (纸本)9781665404266

Text processing, as one of the main issues in the field of artificial intelligence, has received a lot of attention in recent decades. Numerous methods and algorithms are proposed to address the task of semantic textual similarity which is one of the sub-branches of text processing. Due to the special features of the Persian language and its non-standard writing system, finding semantic similarity is an even more challenging task in Persian. On the other hand, producing a proper corpus that can be used for training a model for finding semantic similarities, is of great importance. In this study, the main purpose is to propose a method for measuring the semantic similarity between short Persian texts. To do so, first, we try to build an appropriate corpus, and then propose an efficient approach based on neural networks. the proposed method involves three steps. the first step is data collection and building a parallel corpus. In the next step, namely the pre-processing step, the data is normalized. Finally, Semantic similarity recognition is done by the neural network using vector representations of the words. the suggested model is built upon the produced corpus made of movie and tv show subtitles containing 35266 sentence pairs. the F-measure of the proposed approach on PAN2016 is 75.98% with 4 tags and 98.87% with 2 tags. We also achieved an F-measure of 98.86% for our model tested on the parallel corpus with 2 tags. © 2021 IEEE.

关键词： Text processing

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DSP architectures of Covariance Intersection Fusion Algorithm for Automotive Sensor Fusion

DSP Architectures of Covariance Intersection Fusion Algorith...

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international conference on Computing and Networking Technology (ICCNT)

作者： D.S.L. Praharshita Achala G Pathipati Srihari U. Shripathi Acharya Bethi Pardhasaradhi Engineering Development Group (EDG) India ECE Dept. National Institute of Technology Karnataka India ADAS Dept. Continental Autonomous Mobility India Pvt Ltd India

the data fusion from sensors within the automotive vehicle is vital for improved accuracy and safety. the centralized and information matrix fusion (IMF) algorithms are famous for providing an optimal fusion estimate. However, the IMF is not viable in automotive sensor fusion applications due to the limited bandwidth and low hardware resources. Hence, distributed fusion technology is widely adopted in the automotive sensor applications to achieve high-speed and low-area realizations. this paper proposes three digital signal processing (DSP) architectures for covariance intersection (CI) fusion algorithm: Pipelined-traditional CI, adder-ladder CI, and pipelined adder-ladder CI. the proposed DSP architectures are evaluated with hardware resource consumption (multipliers, adders, and delays), maximum achievable frequency, and latency of the architecture. In addition, proposed CI algorithms for Digital Signal processing (DSP) architectures are compared with IMF DSP architectures. the hardware resources and optimal pipeline stages required for CI with respect to N number of sensors are provided. the traditional pipeline algorithm requires N number of stages where as the proposed pipelined version of adder-ladder CI requires a N−1 pipeline stage with additional 7N−1 and 7N−3 delay elements for even and odd number of sensors to achieve the overall system operating frequency to an operation of multiplier. the proposed DSP architectures are suitable for automotive sensor fusion due to their high operating frequency and low hardware resources.

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