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ComFaaS Distributed: Edge Computing with Function-as-a-Service in parallel Cloud Environments

ComFaaS Distributed: Edge Computing with Function-as-a-Servi...

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international conference on Information and Computer Technologies (ICICT)

作者： Jaden Jinu Lee Judah Nava Hanku Lee Computer Science and Information Systems Minnesota State University Moorhead Moorhead MN

ISBN: (数字)9798350385625

ISBN: (纸本)9798350385632

Function-as-a-Service (FaaS) has emerged as a revolutionary service platform, abstracting the complexities of hardware, operating systems, and web hosting services. this allows developers to focus solely on implementing their service applications, making FaaS an ideal platform for the scalable manipulation of large data sets. Traditionally deployed on the cloud, FaaS now faces a new frontier: the network edge. Leveraging the edge offers several potential benefits, including reduced latency and improved resource utilization, making it a promising approach for efficient FaaS deployment. As the daily volume and complexity of data we handle continues to grow, adopting a parallel computing paradigm has become increasingly important to ensure fast and efficient execution of computational tasks. Addressing this need, ComFaaS Distributed embarks on a comprehensive comparison of the capabilities of parallelized edge and cloud environments for FaaS deployment. Utilizing benchmark programs meticulously crafted to simulate event-triggered scenarios, ComFaaS Distributed aims to provide valuable insights into the performance and potential of FaaS at the edge, paving the way for a future where parallel computing empowers the efficient and scalable processing of ever-growing data volumes.

关键词： Cloud computing Computer architecture parallel processing Benchmark testing Computational efficiency Complexity theory Web sites

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MLIR-to-CGRA: A Versatile MLIR-Based Compiler Framework for CGRAs

MLIR-to-CGRA: A Versatile MLIR-Based Compiler Framework for ...

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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Tianyi Yu Omar Ragheb Stephen Wicklund Jason Anderson Dept. of Electrical and Computer Engineering University of Toronto Toronto Ontario Canada

ISBN: (数字)9798350349634

ISBN: (纸本)9798350349641

Coarse-grained reconfigurable architectures (CGRAs) are programmable hardware platforms with coarse-grained programmable logic blocks and word-wide configurable interconnect. In this paper, we describe a high-level compilation framework tailored for CGRAs. the input to the framework is a C-language program and description of the available CG RA architectural features. this work primarily focuses on automatically handling sequential rectangular loop access patterns. It achieves this by running automated design space exploration (DSE) written within the MLIR compiler representation [7] to leverage both spatial and temporal parallelism inherent in CG RAs. Furthermore, the compiler is engineered to be architecture-agnostic. It employs standard loop (and other) compiler optimization passes alongside CG RA-specific passes to generate a data flow graph (DFG) tailored for a CG RA implementation. In an experimental study, we optimize kernels to increase CG RA mappability and show the impact of automated DSE on the kernel performance. Moreover, the framework eases the task of compilation from software to RISC-V+CGRA hybrid systems.

关键词： Program processors Systems architecture parallel processing Software Space exploration Reconfigurable architectures Kernel

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Strengthening Healthcare Cybersecurity by Optimizing Adversarial Attack Defences in Deep Learning Models using GPU and parallel processing Technologies

Strengthening Healthcare Cybersecurity by Optimizing Adversa...

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international conference on Circuit, Power and Computing Technologies (ICCPCT)

作者： Hridya Venugopal Mary Subaja Christo Department of Networking and Communications SRM Institute of Science and Technology Kattankulathur Campus Chengalpattu Tamilnadu India

ISBN: (数字)9798350372816

ISBN: (纸本)9798350372823

In healthcare, safeguarding patient data integrity is paramount, necessitating robust deep learning models. this research focuses on bolstering the cyber security defenses of these models, particularly against adversarial attacks, through the application of the Localized Adversarial Feature Attack (LAFEAT) technique. Leveraging Graphics processing Units (GPU) and the TensorFlow framework, the study explores algorithmic enhancements like the Fast Gradient Sign Method (FGSM) and Model-Agnostic Meta-Learning (MAML). these techniques perturb input data gradients or adapt model parameters, enhancing resilience against adversarial perturbations. Additionally, Particle Swarm Optimization (PSO), a metaheuristic optimization technique, is examined to fortify defense mechanisms further. parallel processing techniques, utilizing parallel GPU or distributed clusters, are implemented to expedite the optimization process, reducing computational burdens and enhancing scalability. Despite advancements, gaps remain in understanding how these models can be optimized for real-world healthcare applications, particularly in terms of balancing computational efficiency and robustness. the research demonstrates tangible benefits, with a significant 10% increase in success rates against adversarial attacks compared to baseline methods. Moreover, parallel processing implementation results in a 30% reduction in optimization time, improving the efficiency of cyber security defenses for deep learning models in healthcare. these numerical enhancements underscore the research’s value in fortifying healthcare systems against adversarial threats, ensuring the security and integrity of patient data while addressing existing gaps in the optimization of adversarial defenses in healthcare applications. the strengths of this research lie in its robust adversarial attack optimization techniques, integration of parallel processing for efficiency, and application to critical healthcare tasks. Comprehensive

关键词： Deep learning Adaptation models Computational modeling Graphics processing units Medical services parallel processing Data models

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Design of novel macro-cells for next generation ASIC cell library

Design of novel macro-cells for next generation ASIC cell li...

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IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Kiseon Cho Minkyu Song Department of Semiconductor Science Dongguk University Seoul South Korea

ISBN: (纸本)0780365429

this paper describes a design methodology of novel macro-cells for next generation ASIC libraries that has a low-power consumption and high-speed operation. In order to satisfy the desired characteristics, novel architectures of adder, multiplier, and shifter are proposed. Further, automatic layout generation programs are proposed. they are designed on the basis of the standard-cell approach and they generate the layouts of the proposed macro-cells from 8-bit to 64-bit. the proposed macro-cells are designed with a novel compound logic that consists of both CMOS logic and pass-transistor logic. they are fabricated with 0.25 /spl mu/m 1-poly 5-metal CMOS process, and have desired experimental results.

关键词： Application specific integrated circuits Libraries CMOS logic circuits Logic design Automatic logic units Decoding Design methodology Electronic mail CMOS process Data processing

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Development of a versatile low-power 24 GHz phased array front-end in 90 nm CMOS technology

Development of a versatile low-power 24 GHz phased array fro...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： G. Tasselli B. Wang S. Ghamari C. Robert C. Botteron P.A. Farine Electronics and Signal Processing Laboratory École Polytechnique Fédérale de Lausanne Neuchatel Switzerland

this paper deals with the development of a four-channel low-power Phased Array Front-End (PhA-FE) at 24 GHz, targeting both low-power radar sensors and battery powered transceiver applications. Typically, PhA-FEs are power hungry architectures due to multiple parallel RF channels in the FE and complex algorithms for beam steering or high bit-rate demodulation in the digital part. In contrast, we target in this paper applications where both beam steering algorithms and data demodulation are relatively simple and hence achievable with low-power digital signal processing. More specifically, we report on four significant building blocks of the architecture, a Low Noise Amplifier (LNA), a Vector Modulator Phase Shifter (VMPS), a Quadrature Voltage Controlled Oscillator (QVCO) and an Analogue to Digital Converter (ADC) that have been designed the first three in 90nm and the last in 180nm CMOS technology. the LNA shows 24.4 dB gain, 3.4 dB NF and -24.4 dBm input P1dB. the single quadrant VMPS has more than 90° of phase control range and shows less than 0.7 dB of gain variation over phase shifting. the QVCO which consumes less than 32mW, buffer included, has a tuning range of 8%. the 6bit 20 MS/s ADC consumes 1.8mW.

关键词： Gain Transceivers Computer architecture CMOS integrated circuits Radar Microprocessors Sensors

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parallel Subcircuit Extraction Algorithm on GPGPUs

Parallel Subcircuit Extraction Algorithm on GPGPUs

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Che Lun Hung Hsiao Hsi Wang Chun Ting Fu Chia Shin Ou Dept. of Computer Science and Communication Engineering Providence University Taichung Taiwan Dept. of Computer Science & Information Management Providence University Taichung Taiwan Dept. of Computer Science National Tsing Hua University Hsinchu Taiwan

ISBN: (纸本)9781479961245

Subcircuit Extraction plays an important role in Computer-Aided-Design of digital circuits. With the rapid growth of wafer processing technologies, the integration is from very large scale to giga large scale. therefore, to extract sub circuits from such large scale integration is computation-consuming problem. In this paper, we propose a parallel sub circuit extraction algorithm on graphic processing unit. the experimental result shows that the proposed algorithm can achieve over 3x-7x times faster than serial algorithm.

关键词： Graphics processing units Instruction sets Transistors Algorithm design and analysis Logic gates Filtering algorithms Heuristic algorithms

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RISC-V processor-based automatic access floating-point computing accelerated dataflow co-processor

RISC-V processor-based automatic access floating-point compu...

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Science and Technology Innovation (IAECST), international Academic Exchange conference on

作者： Chao-Xing You Qi-Tong Wang Han Zhong Cheng Liu School of Microelectronics Shanghai University China

the Von Neumann and Harvard architectures are very efficient as the common structures of modern computers. However, they reach certain bottlenecks in parallelism, access speed, and power. In this paper, we propose a new architecture to further improve the parallelism and access speed of RISC-V computing system by adding data flow co-processors. the data flow coprocessor in the architecture is further optimized according to the computational characteristics of modern convolutional neural networks. the computation speed of floating- point numbers is increased to further improve the usefulness of the architecture. the data flow coprocessor adds an automatic access mechanism to further relieve the computational pressure on the main processor. Finally, experiments are conducted on the structure with the NEXYS A7 100t FPGA development board to verify the feasibility of the system.

关键词： Computers Technological innovation Computer architecture parallel processing Convolutional neural networks Field programmable gate arrays Coprocessors

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GastroNet FusionAI: Artificial Intelligence Diagnosis of Clinical Gastric Cancer Tumors

GastroNet FusionAI: Artificial Intelligence Diagnosis of Cli...

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IEEE international conference on Information Communication and Signal processing (ICICSP)

作者： Jialun Xu Xiayang Wu Zhenyuan Xu School of Statistics Nanjing Audit University Nanjing China School of Statistics Nanjing University of Posts and Telecommunications Nanjing China

ISBN: (数字)9798350355895

ISBN: (纸本)9798350355901

the significant advancements in natural image processing have sparked widespread interest in applying similar deep learning techniques to medical imaging. Unlike natural images, detecting details in medical images requires capturing finer details, necessitating the use of specially designed network architectures rather than standard ones developed for large-scale, downscaled natural images. Additionally, medical imaging often requires the fusion of images from multiple perspectives to form an accurate diagnosis. therefore, we propose a novel AI algorithm called GastroNet FusionAI, an advanced algorithm specifically designed for gastric cancer diagnosis. It employs an innovative image fusion strategy that effectively integrates images from four different imaging perspectives in gastric cancer detection. this approach not only provides a more comprehensive view but also significantly enhances the accuracy of disease detection by enriching the image content. the development of GastroNet FusionAI aims to improve the early detection rate of gastric cancer, which is crucial for increasing patient survival rates. Gastric cancer is one of the most common types of cancer globally and has a high incidence in certain regions. Despite the enormous potential of AI technology in gastric cancer detection, research on its effectiveness and reliability remains relatively scarce. Existing studies are often limited by small sample sizes, homogeneous datasets, or a lack of rare gastric cancer subtypes. To overcome these challenges, we employed Real-Time Test-Time Augmentation (R-TTA) to expand the original dataset (consisting of 54,706 images) to 273,530 images. this method not only improved the model's learning efficiency but also effectively reduced the risk of overfitting. Our model was trained on a preprocessed dataset from three different hospitals and four different imaging perspectives, and its performance was evaluated using cross-validation to ensure the broad applicability of

关键词： Accuracy Signal processing algorithms Cancer detection Real-time systems Artificial intelligence Medical diagnostic imaging Image fusion Cancer Overfitting Tumors

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Real-time implementation of stereo vision based on optimised normalised cross-correlation and propagated search range on a GPU

Real-time implementation of stereo vision based on optimised...

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IEEE international Workshop on Imaging Systems and Techniques (IST)

作者： Rui Fan Naim Dahnoun Visual Information Laboratory University of Bristol UK Department of Electrical and Electronic Engineering University of Bristol UK

Due to the trade-offs between accuracy and speed, binocular stereo vision is still a challenging task in 3D computer vision research area. In this paper, an efficient stereo matching algorithm is implemented on a state-of-the-art GPU to achieve highly accurate disparity maps in real time for various autonomous vehicle applications. the proposed algorithm is developed from our previous paper, where the search range at row v is propagated from three estimated neighbourhood disparities located at row v + 1. In order to speed up the execution, the prevalent NCC algorithm is optimised by factorising the equation into five independent parts. the computations of hi, H r , aj and a r are accelerated by using the integral images II, Ir, 12 and I r 2. the values of h and a are stored in static program storage for indexing during the stereo matching, which further reduces expensive calculations to help the system perform in real time. the main purpose of this work is to accelerate the processing speed by highly exploiting the parallel computing architectures (OpenMP and CUDA). the performance of the implementation on an NVIDIA GTX 970M GPU is compared with the performance of the implementations on an Intel Core i7-4720HQ CPU using both single thread and multiple threads. the experimental results illustrate that the GPU implementation yields 37 fps when processing the images (resolution: 1242 × 375) from the KITTI database, which is between two and nine times faster than the implementations on the CPU using a different number of threads.

关键词： Graphics processing units Mathematical model Acceleration Real-time systems parallel processing Heuristic algorithms Estimation

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Towards Embedded Heterogeneous FPGA-GPU Smart Camera architectures for CNN Inference 2019

Towards Embedded Heterogeneous FPGA-GPU Smart Camera Archite...

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Proceedings of the 13th international conference on Distributed Smart Cameras

作者： Walther Carballo-Hernández François Berry Maxime Pelcat Miguel Arias-Estrada Department of Images Perception Systems and Robotics Institut Pascal Aubière France Department of Images Institut National des Sciences Appliquées (INSA) des Rennes IETR UMR CNRS Rennes France Department of Computer Science Instituto Nacional de Astrofísica (Óptica y Electrónica (INAOE) Puebla Mexico

ISBN: (纸本)9781450371896

the success of Deep Learning (DL) algorithms in computer vision tasks have created an on-going demand of dedicated hardware architectures that could keep up with the their required computation and memory complexities. this task is particularly challenging when embedded smart camera platforms have constrained resources such as power consumption, processing Element (PE) and communication. this article describes a heterogeneous system embedding an FPGA and a GPU for executing CNN inference for computer vision applications. the built system addresses some challenges of embedded CNN such as task and data partitioning, and workload balancing. the selected heterogeneous platform embeds an Nvidia® Jetson TX2 for the CPU-GPU side and an Intel Altera® Cyclone10GX for the FPGA side interconnected by PCIe Gen2 with a MIPI-CSI camera for prototyping. this test environment will be used as a support for future work on a methodology for optimized model partitioning.

关键词： Internet of things Field Programmable Gate Array (FPGA) Graphic processing Unit (GPU) Deep Learning (DL) Edge Computing processing Elements (PE) Artificial Neural Networks (ANN) Single Instruction Multiple Data Convolutional Neural Networks (CNN) Models of Computation and Architecture Pipelining Heterogeneous Computing parallel Programming

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