检索结果-内蒙古大学图书馆

JParEnt: parallel entropy decoding for JPEG decompression on heterogeneous multicore architectures

CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2017年第15期29卷

作者： Sodsong, Wasuwee Jung, Minyoung Park, Jinwoo Burgstaller, Bernd Yonsei Univ Dept Comp Sci Seoul South Korea

the JPEG format employs Huffman codes to compress the entropy data of an image. Huffman codewords are of variable length, which makes parallel entropy decoding a difficult problem. To determine the start position of a codeword in the bitstream, the previous codeword must be decoded first. We present JParEnt, a new approach to parallel entropy decoding for JPEG decompression on heterogeneous multicores. JParEnt conducts JPEG decompression in two steps: (1)an efficient sequential scan of the entropy data on the CPU to determine the start-positions (boundaries) of coefficient blocks in the bitstream, followed by (2)a parallel entropy decoding step on the graphics processing unit (GPU). the block boundary scan constitutes a reinterpretation of the Huffman-coded entropy data to determine codeword boundaries in the bitstream. We introduce a dynamic workload partitioning scheme to account for GPUs of low compute power relative to the CPU. this configuration has become common with the advent of SoCs with integrated graphics processors (IGPs). We leverage additional parallelism through pipelined execution across CPU and GPU. For systems providing a unified address space between CPU and GPU, we employ zero-copy to completely eliminate the data transfer overhead. Our experimental evaluation of JParEnt was conducted on six heterogeneous multicore systems: one server and two desktops with dedicated GPUs, one desktop with an IGP, and two embedded systems. For a selection of more than 1000JPEG images, JParEnt outperforms the SIMD-implementation of the libjpeg-turbo library by up to a factor of 4.3x, and the previously fastest JPEG decompression method for heterogeneous multicores by up to a factor of 2.2x. JParEnt's entropy data scan consumes 45% of the entropy decoding time of libjpeg-turbo on average. Given this new ratio for the sequential part of JPEG decompression, JParEnt achieves up to97% of the maximum attainable speedup (95% on average). On the IGP-based desktop platform,

关键词： JPEG decoding entropy decoding prefix codes heterogeneous multicores GPU programming

来源：评论

学校读者我要写书评

暂无评论

Designing of a Decentralized Cluster Data Warehouse using Amdahl's and Gustafson's Law

Designing of a Decentralized Cluster Data Warehouse using Am...

引用

international conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)

作者： Ramakrishnan Raman R. Meenakshi Meenakshi Kaul S. Kavitha S. Sujatha Kanapathy Gopalakrishnan Symbiosis Institute of Business Management Pune & Symbiosis International (Deemed University) Pune Maharashtra India Department of Computer Science and Engineering Chennai Institute of Technology Chennai Tamil Nadu India Symbiosis Law School Noida Uttar Pradesh Symbiosis International (Deemed University) Pune Maharashtra India Department of Electronics and Communication Engineering Hindusthan Institute of Technology Coimbatore Tamil Nadu India Department of Biomedical Engineering Saveetha School of Engineering Saveetha Institute of Medical and Technical Sciences Saveetha University Chennai Tamil Nadu India Cambrdge Institute of Technology Bengaluru Karnataka India

Decentralized cluster data warehouses are popular owing to their scalability and availability. Performance and resource consumption must be considered while creating such systems. Amdahl's law argues that the proportion of the workload that cannot be parallelized limits a system's speedup. this law affects system design in decentralized cluster data warehousing. In creating a decentralized cluster data warehouse, Amdahl's law requires detecting and evaluating bottlenecks in data input, storage, processing, and query execution. Designers may improve parallelizable components by understanding non-parallelizable components. A decentralized cluster data warehouse needs data propagation. Keeping frequently accessible data close may impair system performance. this requires exact data partition, replication, and cluster node data placement. Decentralized cluster data warehouses need technical, organizational, and governance concerns. Data security, privacy, regulatory compliance, and accessibility are examples. John Gustafson and Edwin Barsis' Gustafson's Law stresses parallel computing's scalability and workload rise. Gustafson's Law allows scaling up the issue and using more computer resources to handle higher workloads, unlike Amdahl's Law. the law shows that as the issue size increases, the percentage of the program that may be processed in parallel becomes a bigger fraction of the entire execution time, improving efficiency and speedup. Gustafson's Law promotes reducing execution time by dividing task over numerous processors. this abstract compares Gustafson's Law with Amdahl's Law, revealing parallel computing's advantages for bigger problem instances and the impact of increasing workload in parallel efficiency.

关键词：

来源：评论

学校读者我要写书评

暂无评论

A customized convolutional neural network structure design based on Field-Programmable Gate Array

A customized convolutional neural network structure design b...

引用

Computer Information Science and Application Technology (CISAT), international conference on

作者： Jiahong Zhang Dejun Yin Nanjing University of Science and Technology Nanjing China

ISBN: (数字)9798350375107

ISBN: (纸本)9798350375114

In this paper, different hardware deployment schemes are designed to accelerate the overall reasoning process of convolutional neural network according to the characteristics of large amount of calculation in convolution layer and large amount of parameters in linear layer. For convolutional neural networks with fewer layers, the LUT multiplication circuit is used instead of the DSP multiplication and the parameters are fixed in the circuit to reduce the dependence on DSP and ROM resources. this makes it possible to achieve higher parallelism reasoning on FPGAs with fewer resources. In this paper, a reduced-order convolutional neural network is trained based on the MNIST training set. After 8bit quantization, it is deployed to the FPGA and the inference speed reaches $\mathbf{7. 3 5 6}$ us, which is 339 times faster than that of the CPU.

关键词： Training Quantization (signal) Convolution parallel processing throughput Cognition Table lookup Convolutional neural networks Field programmable gate arrays Read only memory

来源：评论

学校读者我要写书评

暂无评论

High throughput Hardware for Hoeffding Tree Algorithm with Adaptive Naive Bayes Predictor

High Throughput Hardware for Hoeffding Tree Algorithm with A...

引用

international conference for Convergence of Technology (I2CT)

作者： Ashin Antony Devi A Kuruvilla Varghese Indian Institute Of Science Bangalore India

Hoeffding tree algorithm is a popular online decision tree algorithm capable of learning from huge data streams. the algorithm involves complex time consuming computations in the leaves of the tree for each data instance. these computations involve a lot of parallelisms which can be exploited and implemented in a field programmable gate array to achieve speedup. this paper presents a hardware accelerator for Hoeffding tree algorithm with adaptive naive bayes predictor in the leaves. the proposed system is capable of accelerating data streams with both nominal and numeric attributes using minimum hardware resources for huge datasets. It is implemented on a Xilinx VC707 board based on Virtex-7 XC7VX485T field programmable gate array. the implemented system is about 9x faster than StreamDm(C++), a well known reference software implementation for the standard forest cover type dataset.

关键词： Vegetation parallel processing Logic gates Prediction algorithms throughput Hardware Table lookup

来源：评论

学校读者我要写书评

暂无评论

RISC-V processor-based automatic access floating-point computing accelerated dataflow co-processor

RISC-V processor-based automatic access floating-point compu...

引用

Science and Technology Innovation (IAECST), international Academic Exchange conference on

作者： Chao-Xing You Qi-Tong Wang Han Zhong Cheng Liu School of Microelectronics Shanghai University China

the Von Neumann and Harvard architectures are very efficient as the common structures of modern computers. However, they reach certain bottlenecks in parallelism, access speed, and power. In this paper, we propose a new architecture to further improve the parallelism and access speed of RISC-V computing system by adding data flow co-processors. the data flow coprocessor in the architecture is further optimized according to the computational characteristics of modern convolutional neural networks. the computation speed of floating- point numbers is increased to further improve the usefulness of the architecture. the data flow coprocessor adds an automatic access mechanism to further relieve the computational pressure on the main processor. Finally, experiments are conducted on the structure with the NEXYS A7 100t FPGA development board to verify the feasibility of the system.

关键词： Computers Technological innovation Computer architecture parallel processing Convolutional neural networks Field programmable gate arrays Coprocessors

来源：评论

学校读者我要写书评

暂无评论

X-Ray Computed Tomography Applied to Objects of Cultural Heritage: Porting and Testing the Filtered Back-Projection Reconstruction Algorithm on Low Power Systems-on-Chip

X-Ray Computed Tomography Applied to Objects of Cultural Her...

引用

Euromicro conference on parallel, Distributed and Network-Based processing

作者： Elena Corni Lucia Morganti Maria Pia Morigi Rosa Brancaccio Matteo Bettuzzi Giuseppe Levi Eva Peccenini Daniele Cesini Andrea Ferraro Department of Physics and Astronomy University of Bologna Bologna Italy Bologna Section Italian Institute for Nuclear Physics (INFN) Bologna Italy Enrico Fermi Center for Study and Research Roma Italy CNAF Section Italian Institute for Nuclear Physics (INFN) Bologna Italy

the embedded and high-performance computing (HPC) sectors, that in the past were completely separated, are now somehow converging under the pressure of two driving forces: the release of less power consuming server processors and the increased performance of the new low power Systems-on-Chip (SoCs) developed to meet the requirements of the demanding mobile market. this convergence allows the porting to low power embedded architectures of applications that were originally confined to traditional HPC systems. In this paper, we present our experience of porting the Filtered Back-projection Algorithm to a low power, low cost system-on-chip, the NVIDIA Tegra K1, which is based on a quad core ARM CPU and on a NVIDIA Kepler GPU. this Filtered Back-projection Algorithm is heavily used in 3D Tomography reconstruction software. the porting has been done exploiting various programming languages (i.e. OpenMP, CUDA) and multiple versions of the application have been developed to exploit both the SoC CPU and GPU. the performances have been measured in terms of 2D slices (of a 3D volume) reconstructed per time unit and per energy unit. the results obtained with all the developed versions are reported and compared with those obtained on a typical x86 HPC node accelerated with a recent NVIDIA GPU. the best performances are achieved combining the OpenMP version and the CUDA version of the algorithm. In particular, we discovered that only three Jetson TK1 boards, equipped with Giga Ethernet interconnections, allow to reconstruct as many images per time unit as a traditional server, using one order of magnitude less energy. the results of this work can be applied for instance to the construction of an energy-efficient computing system of a portable tomographic apparatus.

关键词： Graphics processing units Image reconstruction Computer architecture Filtering algorithms Computed tomography Radiography

来源：评论

学校读者我要写书评

暂无评论

Efficient simulation of biological neural networks on massively parallel supercomputers with hypercube architecture 93

Efficient simulation of biological neural networks on massiv...

引用

Proceedings of the 7th international conference on Neural Information processing Systems

作者： Ernst Niebur Dean Brettle Computation and Neural Systems California Institute of Technology Pasadena CA Booz Allen and Hamilton Inc. McLean VA

We present a neural network simulation which we implemented on the massively parallel Connection Machine 2. In contrast to previous work, this simulator is based on biologically realistic neurons with nontrivial single-cell dynamics, high connectivity with a structure modelled in agreement with biological data, and preservation of the temporal dynamics of spike interactions. We simulate neural networks of 16,384 neurons coupled by about 1000 synapses per neuron, and estimate the performance for much larger systems. Communication between neurons is identified as the computationally most demanding task and we present a novel method to overcome this bottleneck. the simulator has already been used to study the primary visual system of the cat.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Towards Embedded Heterogeneous FPGA-GPU Smart Camera architectures for CNN Inference 2019

Towards Embedded Heterogeneous FPGA-GPU Smart Camera Archite...

引用

Proceedings of the 13th international conference on Distributed Smart Cameras

作者： Walther Carballo-Hernández François Berry Maxime Pelcat Miguel Arias-Estrada Department of Images Perception Systems and Robotics Institut Pascal Aubière France Department of Images Institut National des Sciences Appliquées (INSA) des Rennes IETR UMR CNRS Rennes France Department of Computer Science Instituto Nacional de Astrofísica (Óptica y Electrónica (INAOE) Puebla Mexico

ISBN: (纸本)9781450371896

the success of Deep Learning (DL) algorithms in computer vision tasks have created an on-going demand of dedicated hardware architectures that could keep up with the their required computation and memory complexities. this task is particularly challenging when embedded smart camera platforms have constrained resources such as power consumption, processing Element (PE) and communication. this article describes a heterogeneous system embedding an FPGA and a GPU for executing CNN inference for computer vision applications. the built system addresses some challenges of embedded CNN such as task and data partitioning, and workload balancing. the selected heterogeneous platform embeds an Nvidia® Jetson TX2 for the CPU-GPU side and an Intel Altera® Cyclone10GX for the FPGA side interconnected by PCIe Gen2 with a MIPI-CSI camera for prototyping. this test environment will be used as a support for future work on a methodology for optimized model partitioning.

关键词： Internet of things Field Programmable Gate Array (FPGA) Graphic processing Unit (GPU) Deep Learning (DL) Edge Computing processing Elements (PE) Artificial Neural Networks (ANN) Single Instruction Multiple Data Convolutional Neural Networks (CNN) Models of Computation and Architecture Pipelining Heterogeneous Computing parallel Programming

来源：评论

学校读者我要写书评

暂无评论

Research on a Real-time Dynamic Monitoring System based on PMU

Research on a Real-time Dynamic Monitoring System based on P...

引用

2019 7th international conference on Machinery,Materials and Computing Technology(ICMMCT 2019)

作者： Liu Wei Electrical Engineering College Jilin Technology College of Electronic Information

With the development of real-time dynamic monitoring system,each regional dynamic monitoring system is relatively independent,and has its own photo independent scheduling *** accommodate this partition management model,state estimation should use a distributed parallel *** on the dynamic spread algorithm and the parallel algorithm of lapped distribution,a new dynamic state estimation algorithm for distributed real-time dynamic monitoring system based on phasor measurement unit(PMU) is *** algorithm uses a small number of PMU measurement points to truly realize the parallel computing of each subsystem,avoiding the process of serial waiting by the original *** with the measurement data preprocessing and the comparison of the matrix weighting,the calculation speed is accelerated and the numerical precision and stability are ***,the simulation results of IEEE 14 nodes are given,and the effectiveness and superiority of the algorithm are verified.

关键词： Phasor Measurement Unit Dynamic State Estimation Distributed processing Dynamic Monitoring System

来源：评论

学校读者我要写书评

暂无评论

DEEP IMAGE CLUSTERING USING CONVOLUTIONAL AUTOENCODER EMBEDDING WIth INCEPTION-LIKE BLOCK

DEEP IMAGE CLUSTERING USING CONVOLUTIONAL AUTOENCODER EMBEDD...

引用

IEEE international conference on Image processing

作者： Qiang Wang Jiaqing Xu Rongchun Li Peng Qiao Ke Yang Shijie Li Yong Dou National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China School of Computer National University of Defense Technology Changsha China

Image clustering is one of the challenging tasks in machine learning, and has been extensively used in various applications. Recently, various deep clustering methods has been proposed. these methods take a two-stage approach, feature learning and clustering, sequentially or jointly. We observe that these works usually focus on the combination of reconstruction loss and clustering loss, relatively little work has focused on improving the learning representation of the neural network for clustering. In this paper, we propose a deep convolutional embedded clustering algorithm with inception-like block (DCECI). Specifically, an inception-like block with different type of convolution filters are introduced in the symmetric deep convolutional network to preserve the local structure of convolution layers. We simultaneously minimize the reconstruction loss of the convolutional autoencoders with inception-like block and the clustering loss. Experimental results on multiple image datasets exhibit the promising performance of our proposed algorithm compared with other competitive methods.

关键词： Convolutional codes Convolution Clustering algorithms Image reconstruction Decoding Clustering methods Task analysis

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：