Describes the architecture of a mesh array smart sensor, in close relation withthe algorithms to be carried out by it. On the one hand, a monolithic implementation of the mesh array is a logical consequence of its de...
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Describes the architecture of a mesh array smart sensor, in close relation withthe algorithms to be carried out by it. On the one hand, a monolithic implementation of the mesh array is a logical consequence of its design requirements within the framework of full custom integration. On the other hand, today's implementations are limited to Boolean picture processing and binary picture memorization if sensible size pictures are to be handled. Nevertheless, the validity of these choices is confirmed by a 50-mm/sup 2/ area (60*60PE) chip which has been laid out in a 2- mu m two-metal CMOS technology.< >
this conference proceedings contains 71 papers. the following topics are dealt with: resource scheduling and management, network design, data alloca tion, communication protocols, remote execution protocols, interconn...
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ISBN:
(纸本)0818608013
this conference proceedings contains 71 papers. the following topics are dealt with: resource scheduling and management, network design, data alloca tion, communication protocols, remote execution protocols, interconnection networks, database concurrency control, load balancing, operating system concurrency control, performance enhancement schemes, language support, time and synchronization, distribution query processing, algorithms, network implementation, distributed architectures, models for concurrent activities, performance measurements and tools, highly available databases, and performance evaluation of communication architectures.
the following topics are dealt with: resource scheduling and management, network design, data allocation, communication protocols, remote execution protocols, interconnection networks, database concurrency control, lo...
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ISBN:
(纸本)0818608013
the following topics are dealt with: resource scheduling and management, network design, data allocation, communication protocols, remote execution protocols, interconnection networks, database concurrency control, load balancing, operating system concurrency control, performance enhancement schemes, language support, time and synchronization, distribution query processing, algorithms, network implementation, distributed architectures, models for concurrent activities, performance measurements and tools, highly available databases, and performance evaluation of communication architectures.
there are numerous places within the general task framework of a computer music workstation where multiprocessing solutions are a natural way to overcome the diversity of tasks and the tight scheduling constraints of ...
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the DUAL network is based on multi-microprocessor nodes mounted on a Multibus chassis and interlinked by means of 140 Mb/s fiber-optic trunks. the DUAL ring is installed in a 160-hectare campus and serves as the backb...
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ISBN:
(纸本)0818608013
the DUAL network is based on multi-microprocessor nodes mounted on a Multibus chassis and interlinked by means of 140 Mb/s fiber-optic trunks. the DUAL ring is installed in a 160-hectare campus and serves as the backbone network to a number of Ethernet TM, ISO 8802. X LANs and X25 networks. In addition to acting as a backbone network to other existing networks, DUAL itself provides LAN, X25 and other services. It has been designed to offer not only conventional network services (datagram and connections) but also multicast (radios and conferences) and synchronization primitives (semaphores) in support of distributed and parallelprocessing on a large scale.
Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. this will have a profound impact on the design rules for ...
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Rule-based systems appear to be capable of exploiting large amounts of parallelism, because it is possible to match each rule to the data memory in parallel. It is pointed out that in practice the speedup from paralle...
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ISBN:
(纸本)081860719X
Rule-based systems appear to be capable of exploiting large amounts of parallelism, because it is possible to match each rule to the data memory in parallel. It is pointed out that in practice the speedup from parallelism is quite limited, less than 10-fold. the reasons for the small speedup are: (1) the small number of rules relevant to each change to data memory;(2) the large variation in the processing required by the relevant rules;and (3) the small number of changes made to data memory between synchronization steps. To obtain this limited factor of 10-fold speedup, it is necessary to exploit parallelism at a very fine granularity. It is suggested that a suitable architecture to exploit such fine-grain parallelism is a bus-based shared-memory multiprocessor with 32-64 processors. Using such a multiprocessor (with individual processors working at 2 MIPS), it is possible to obtain execution speeds of about 3800 rule-firings/s. this speed is significantly higher than that obtained by other proposed parallel implementations of rule-based systems.
To date, simulation has been the primary method used to support hardware logic design. In particular, there has been little that could support such design from the system level, such as a language to describe processi...
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Approaching rapidly on the horizon is a change to parallel architecture in digital computers that has the potential for multiplying the speed of execution achieved in serial architectures. the departure from serial op...
Approaching rapidly on the horizon is a change to parallel architecture in digital computers that has the potential for multiplying the speed of execution achieved in serial architectures. the departure from serial operations provides rather obvious improvements in execution times for operations that are repetitive and that can be performed independently of each other. Such operations arise frequently in signal processing programs and in mathematical programming algorithms. Of interest to this conference is the impact of the new architectures on the practice of simulation - particularly simulations of large physical systems. A large number of questions can be raised (but few answered) on the impact of the new machines on simulation model designs, languages, data base manipulation, and other questions on the general utility of such machines for simulation problem solving. Moreover, it is likely that the new machines will influence the design of simulation experiments, random number generation, strategies for statistical iterations, sensitivity analyses, and variance reduction methods. Because of the interdisciplinary nature of these topics a dialog between simulation practitioners and computer technology developers will grow in importance. Several panelists, consisting of a mixture of simulation practitioners and computer scientists will describe their recent experiences in simulating systems on parallel computer configurations, highlighting efficiency comparisons and speculating on the general utility of such machines for simulation enterprises.
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