this research addresses the topic of inclusion with emphasis on Deaf people, exposing the concept of the application of engineering systems through the design of a voice graphing software developed in LabView74; th...
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ISBN:
(数字)9798350367447
ISBN:
(纸本)9798350367454
this research addresses the topic of inclusion with emphasis on Deaf people, exposing the concept of the application of engineering systems through the design of a voice graphing software developed in LabView® that is used as a practice tool in the oralization process of people born Deaf but withthe ability to phonate, which, according to global data, places them at a social, cultural, labor and economic disadvantage. this tool works as a technological support parallel to the therapeutic process carried out by specialists, aiming to provide support that encourages the practice of vocalization and oralization using the software presented in this article. the results collected in this work are the product of a multidisciplinary research that began in 2019, which continues in a complementary process of testing and adjustments according to the observations of users and speech therapists. It is these people together who provide feedback on the design withthe aim of obtaining a functional application that seeks to irrigate Technology Applied to Inclusion and Bioinformatics in Educational Institutions and in society in general. the efforts of this research contribute to objectives 3 and 10 of the 2030 Agenda for Sustainable Development, relating to Health and Well-being and Reduction of Inequalities.
An ultra-low power DFT architecture suitable for MIMO-OFDM applications & it was introduced in this study. Several radix such as 8/16/32 dependent optimization methods are performed to create variable lengths of 4...
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ISBN:
(数字)9798350394474
ISBN:
(纸本)9798350394481
An ultra-low power DFT architecture suitable for MIMO-OFDM applications & it was introduced in this study. Several radix such as 8/16/32 dependent optimization methods are performed to create variable lengths of 4k/8k points, a necessity in today's 4G and 5G communication technologies, which are plagued by a number of power and performance concerns with DFT processors. these technologies are widely used but have a higher energy footprint than others. Consequently, this work uses a novel approach called "SBOX" and the concept of parallelism to boost performance and reduce power consumption, all of which are essential for an advanced DFT architecture. parallelism and the proposed SBOX model allow for fewer multiplications and faster processing times. Cadence-allegro-17.2 is used for the design and verification of the full implementation; this software is also used for simulation, synthesis, layout, and power analysis. the area required for 8-point s-box DFT is 105.15 um2, it requires 7mW of power, and it can achieve a throughput of 59.33GBPS. In addition, the throughput of 57.33GBPS may be achieved by 16-point s-box DFT with a footprint of 123.35um2, using 9mW of power. Also, the throughput of 32-point s-box DFT is 56.45GBPS on a chip that uses 10.24 mW and occupies 132.35um2. With MIMO in 5G technology, this layout becomes more practical for usage in telecommunications. the performance is enhanced over existing architecturesthanks to the optimized radix 8 s-box DFT.
this paper presents an improved parallelprocessing uninterruptible power supply (UPS) for a strong grid using a bidirectional voltage-controlled voltage source inverter (VCVSI). To maintain the load voltage at the de...
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this paper presents an improved parallelprocessing uninterruptible power supply (UPS) for a strong grid using a bidirectional voltage-controlled voltage source inverter (VCVSI). To maintain the load voltage at the desired value and to control the active power flow between the VCVSI and grid, the amplitude and phase angle of the inverter output voltage (power angle) must be controlled. Selecting the power angle operating range is an important factor which has a direct effect on various parameters, such as the size of a decoupling inductor, grid power factor and the power ratings of VCVSI components. It is shown how the optimum power angles can be chosen and by restricting the operation of this, the power factor can be maintained above 0.9 at different loads and operating conditions. the paper examines the steady state modeling and analysis of a single phase parallelprocessing UPS while maintaining a high system power factor under different conditions. Experimental and simulation results of a prototyped 1KVA VCVSI confirms the validity of the proposed method.
Filtered Back-Projection (FBP) is a fundamental compute intense algorithm used in tomographic image reconstruction. Cone-Beam Computed Tomography (CBCT) devices use a cone-shaped X-ray beam, in comparison to the paral...
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ISBN:
(数字)9781450384421
ISBN:
(纸本)9781665483902
Filtered Back-Projection (FBP) is a fundamental compute intense algorithm used in tomographic image reconstruction. Cone-Beam Computed Tomography (CBCT) devices use a cone-shaped X-ray beam, in comparison to the parallel beam used in older CT generations. Distributed image reconstruction of cone-beam datasets typically relies on dividing batches of images into different nodes. this simple input decomposition, however, introduces limits on input/ output sizes and scalability. We propose a novel decomposition scheme and reconstruction algorithm for distributed FPB. this scheme enables arbitrarily large input/output sizes, eliminates the redundancy arising in the end-to-end pipeline and improves the scalability by replacing two communication collectives with only one segmented reduction. Finally, we implement the proposed decomposition scheme in a framework that is useful for all current-generation CT devices (7th gen). In our experiments using up to 1024 GPUs, our framework can construct 4096 3 volumes, for real-world datasets, in under 16 seconds (including I/O).
Computational systems are nowadays composed of basic computational components that share multiprocessors and coprocessors of different types, typically several graphics processing units (GPUs) or many integrated cores...
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Computational systems are nowadays composed of basic computational components that share multiprocessors and coprocessors of different types, typically several graphics processing units (GPUs) or many integrated cores (MICs), and those computational components are combined in heterogeneous clusters of nodes with different characteristics, including coprocessors of different types, with varying numbers of nodes at different speeds. the software previously developed and optimized for simpler system needs to be redesigned and reoptimized for these new, more complex systems. the adaptation to hybrid multicore+multiGPU and multicore+multiMIC of autotuning techniques for basic linear algebra routines is analyzed. the matrix-matrix multiplication kernel, which is optimized for different computational system components through guided experimentation, is studied. the routine is installed for each node in the cluster, and the information generated from individual installations may be used for a hierarchical installation in a cluster. the basic matrix-matrix multiplication may, in turn, be used inside higher level routines, which delegate their efficient execution to the optimization of the lower level routine. Experimental results are satisfactory in different multicore+multiGPU and multicore+multiMIC systems. So the guided search of execution configurations for satisfactory execution times proves to be a useful tool for heterogeneous systems, where the complexity of the system means a correct use of highly efficient routines and libraries is difficult.
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