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检索条件"任意字段=7th International Conference on Algorithms and Architectures for Parallel Processing"

共 2981 条记录，以下是21-30 订阅

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An Efficient Task-parallel Pipeline Programming Framework 24

An Efficient Task-Parallel Pipeline Programming Framework

引用

7th international conference on High Performance Computing in Asia-Pacific Region (HPC Asia)

作者： Chiu, Cheng-Hsiang Xiong, Zhicheng Guo, Zizheng Huang, Tsung-Wei Lin, Yibo Univ Wisconsin Madison Madison WI 53706 USA Tsinghua Univ Beijing Peoples R China Peking Univ Beijing Peoples R China

ISBN: (纸本)9798400708893

the pipeline is a fundamental pattern to parallelize a series of stage tasks over a sequence of data in loops. Mainstream pipeline programming frameworks count on data abstractions to perform pipeline scheduling. Although this design is convenient for data-centric parallel applications, it is not efficient for algorithms that only exploit task parallelism in the pipeline. To address the limitation, we introduce a new task-parallel pipeline programming framework called Pipeflow. Pipeflow separates data abstractions and task scheduling, enabling a more efficient implementation of task-parallel pipeline algorithms than existing frameworks. We have evaluated Pipeflow on both micro-benchmarks and real-world applications. For example, in a timing analysis workload that explores pipeline parallelism to speed up the runtime performance, the Pipeflow's implementation outperforms the oneTBB's implementation up to 110.33% faster.

关键词： Task-parallel Pipeline parallelism Pipeline Scheduling

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Research on optimization of stream data processing algorithm for multi-core processor based on MapReduce 7

Research on optimization of stream data processing algorithm...

引用

7th international conference on Automation Electronics and Electrical Engineering

作者： Shang, Yingmei Wang, Genjie Ruan, Jing Anhui Sanlian Univ Hefei Anhui Peoples R China

ISBN: (纸本)9798350377040;9798350377033

With the rapid development of information technology and the popularization of the Internet, streaming data processing has become one of the core tasks of big data analysis. With their parallel computing capabilities, multi-core processors show great potential in efficiently processing massive streams of data. However, the traditional streaming data processing algorithm often faces the problems of uneven resource allocation, unbalanced load and high communication overhead when facing multi-core architecture, which limits the overall performance of the system. Based on MapReduce programming model, this paper discusses the optimization strategy of streaming data processing algorithm in multi-core processor environment. Firstly, this paper analyzes the limitations of the existing MapReduce framework in the stream data processing scenario, including the delay increase caused by batch processing tendency and the lack of adaptability to dynamic data flow. then, an improved Partitioning Strategy is proposed, which can dynamically adjust task allocation according to data flow characteristics, ensure load balancing among cores, and minimize cross-core communication costs. In order to further improve the processing efficiency, this paper also designs a kernel processor stream data processing algorithm based on MapReduce-partitioning strategy, which can dynamically adjust the task priority and optimize the execution order according to real-time performance monitoring information. the experimental results show that the proposed optimization method not only effectively improves the speed of upstream data processing, but also enhances the stability and reliability of the system, which provides theoretical support and technical reference for future large-scale streaming data analysis.

关键词： multi-core processor MapReduce load balancing partition strategy

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Audio signal Enhancement based on amplitude and phase deep learning model 7

Audio signal Enhancement based on amplitude and phase deep l...

引用

IEEE 7th international conference on Advanced Technologies, Signal and Image processing (ATSIP)

作者： Benneila, Mahrez Hadji, Salah ben Messouad, Mouhamed Anouar Natl Engineers Sch Tunis Lab Signal Images & Technol Informat LR SITI ENIT Tunis Tunisia CERTn Borj Hamm Lif Lab Nanomat & Energy Lanser Tunis Tunisia

ISBN: (纸本)9798350351491;9798350351484

In this work, we apply an approach based on simultaneous enhancement of the amplitude and phase time-frequency representation of a composite audio signal with two datasets, namely the Voice Bank+Demand and the NTCD TIMIT datasets. the approach is based on an encoder and a decoder connected by transformers having a convolution module. the encoder uses both amplitude and phase spectra as input, while the decoder has two parts one of parallel amplitude mask and the other is a phase decoder. thus allowing direct recovery of clean amplitude spectra and also clean enveloped phase spectra, its activation function is a sigmoid learnable and it estimates the phase in parallel. Like all neural networks there are losses at several levels such as: amplitude, phase, and short-term complex, without forgetting the temporal waveforms. All these losses are used jointly in training the model implemented, the validation of this model is done on the two datasets and the experimental results gave a PESQ of 3.5 for the Voice Bank+demand and a PESQ of 3.22 for NTCD-TIMIT.

关键词： speech enhancement encoder-decoder parallel denoising magnitude spectra phase spectra

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Massively parallel EEG algorithms for Pre-exascale architectures

Massively Parallel EEG Algorithms for Pre-exascale Architect...

引用

29th international conference on parallel and Distributed Computing (Euro-Par)

作者： Wang, Zeyu Juhasz, Zoltan Univ Pannonia Veszprem Hungary

ISBN: (纸本)9783031488023;9783031488030

High-density EEG is a non-invasive measurement method with millisecond temporal resolution that allows us to monitor how the human brain operates under different conditions. the large amount of data combined with complex algorithms results in unmanageable execution times. Large-scaleGPU parallelism provides the means to drastically reduce the execution time of EEG analysis and bring the execution of large cohort studies (over thousand subjects) within reach. this paper describes our effort to implement various EEG algorithms for multiGPUpre-exascale supercomputers. Several challenges arise during thiswork, such as the high cost of data movement and synchronisation compared to computation. A performance-oriented end-to-end design approach is chosen to develop highlyscalable, GPU-only implementations of full processing pipelines and modules. Work related to the parallel design of the family of Empirical Mode Decomposition algorithms is described in detail with preliminary performance results of single-GPU implementations. the research will continue with multi-GPU algorithm design and implementation aiming to achieve scalability up to thousands of GPU cards.

关键词： EEG Pre-exascale computing GPU

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Towards understanding and mitigating the hallucinations in NLP and Speech 24

Towards understanding and mitigating the hallucinations in N...

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7th ACM India Joint international conference on Data Science and Management of Data (CODS-COMAD) / 11th ACM IKDD CODS conference / 29th COMAD conference

作者： Mittal, Ashish Murthy, Rudra, V Kumar, Vishwajeet Bhat, Riyaz Indian Inst Technol IBM Res Bombay Maharashtra India IBM Res Bangalore Karnataka India

ISBN: (纸本)9798400716348

With the recent advances in natural language processing, thanks to deep learning architectures such as the transformer, the performances on many of the challenging NLP tasks such as question answering, machine translation, abstractive summarization, etc. have exponentially improved. However, with the state-of-the-art models, it is observed that even though these models generate natural and fluent-looking text but many times they are unfaithful and may contain facts/information that is irrelevant or not supported by the input. this phenomenon is referred to in the literature as a hallucination. A similar phenomenon is observed in end-to-end speech recognition systems, where the portion of the output text is having different acoustics when compared to the corresponding speech signal. In this tutorial, we introduce the problem of hallucinations in various Speech and NLP tasks such as machine translation, summarization and speech recognition. We categorize the hallucinations observed in this model and describe the techniques to quantify them. Next, we describe recent techniques to overcome hallucinations for many of these tasks. We draw the attention of the AI community to the potential problems of hallucinations in NLP and speech.

关键词： Natural language processing systems

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Efficient OAM-Based Programmable Hardware Accelerator Architecture 14

Efficient OAM-Based Programmable Hardware Accelerator Archit...

引用

14th international conference on Advanced Computer Information Technologies, ACIT 2024

作者： Melnyk, Viktor Melnyk, Anatoliy Rahma, Mohammad Lviv Polytechnic National University Department of Information Technologies Security Lviv Ukraine John Paul Ii Catholic University of Lublin Faculty of Natural and Technical Sciences Lublin Poland It Step University Lviv Ukraine Al-Mustaqbal University Computer Engineering Department Babylon Iraq

ISBN: (纸本)9798350350036

Today, there are a large number of tasks that involve processing data in the form of arrays. these include, in particular, algorithms for fast orthogonal transformations and cryptographic protection of information, whose structure remains consistent regardless of the data. For such algorithms, hardware accelerators are usually used to improve the system performance characteristics. their architecture traditionally involves an addressable memory, which limits their productivity increase. An efficient programmable hardware accelerator architecture based on conflict-free parallel ordered access memory (OAM) that is based on the corresponding model of computing is proposed in this paper. the approach to OAM-based programmable parallel hardware accelerator design is described and its structure is proposed. the benefits of the proposed programmable hardware accelerator architecture compared to existing conventional architectures are emphasized. © 2024 IEEE.

关键词： parallel architectures

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Increased throughput and Power Efficient Multi-Path 1024-Point Radix-22 FFT Processor for Signal processing Applications 7

Increased Throughput and Power Efficient Multi-Path 1024-Poi...

引用

7th international conference on Computing in Engineering and Technology, ICCET 2022

作者： thokala, Mohan Rao Gopi, Telagamalla Department of Electronics and Communication Engineering Siddhartha Institute of Engineering and Technology Telangana State Hyderabad501506 India

ISBN: (纸本)9781839537042

FFT processor used for high-speed signal processing applications, such that to meet the required high-speed applications, FFT processor uses pipeline and parallel processing algorithms to provide such high-speed applications, pipelining techniques such as delay feedback and delay commutation technique are used, for this radix -2k algorithm based FFT processor to provide parallel path signal processing implemented pipeline architectures are used. For high throughput radix-22 radix-23 radix-24 algorithms are used. they reduce both the number of adders and the number of *** processor occupies an area of 3.6mm2 and operating supply voltage of 0.4V-1V, and at a frequency of 600MHz. By taking advantage of Radix-4 algorithm techniques, the processor is implemented with four parallel path signal processing without overhead of hardware compared to the two-path processor. the implemented processor takes less power, approximately 14%, compared to the two-path FFT processor, and the area reduces by 20% using Radix-22 algorithm techniques. Simulation results are observed using Xilinx ISE 14.7 Design Suite using Verilog-HDL coding. © 2022 the Institution of Engineering and Technology.

关键词： Fast Fourier transforms

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Dynamic Multi-bit parallel Computing Method Based on Reconfigurable Structure 23rd

Dynamic Multi-bit Parallel Computing Method Based on Reconfi...

引用

23rd international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Jiang, Lin Liu, Shuai Zhu, Jiayang Shan, Rui Li, Yuancheng Xian Univ Sci & Technol Xian 710600 Shaanxi Peoples R China Xian Univ Posts & Telecommunicat Xian 710100 Shaanxi Peoples R China

ISBN: (纸本)9789819708000;9789819708017

Reconfigurable architecture has great potential in computation-intensive and memory-intensive applications due to its flexible information configuration. Aiming at the problem of low computing efficiency caused by the inconsistency between different granularity data and the underlying hardware structure in applications such as communication baseband signal processing, a parallel computing method supporting multi-bit data is proposed, and a dynamic granularity configuration structure used this method is designed based on reconfigurable array processors. the structure divides the calculation granularity into 8 bits, 16 bits, and 32 bits, and realizes four functions: data-combination, data-splitting, parallel-addition, and parallel-multiplication. these features increase the parallelism and flexibility of array structures. the experimental results show that the speedup ratio can reach 1.5 within a certain error range, the running time is reduced by about 20%, and the code complexity is also significantly reduced. In addition, the maximum operating frequency of the dynamic configuration circuit is 133.5 MHz by FPGA comprehensive implementation, which can realize the dynamic configuration of different granularity data in the calculation and achieve parallel computing of multi-bit data.

关键词： Reconfigurable Architecture parallel Computing Computing Granularity Array Processor

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BachLedger: Orchestrating parallel Execution with Dynamic Dependency Detection and Seamless Scheduling 30

BachLedger: Orchestrating Parallel Execution with Dynamic De...

引用

30th IEEE international conference on parallel and Distributed Systems, ICPADS 2024

作者： Yang, Yi Shang, Guangyong Qi, Guangpeng Ma, Zhen Liu, Yaxiong Tian, Jiazhou Duan, Aocheng Zhang, Meng Li, Jingying Ding, Xuan Tsinghua University School of Software Beijing China Inspur Yunzhou Industrial Internet Co. Ltd Shandong Jinan China Xidian University School of Cyber Engineering Shaanxi Xi'an China

ISBN: (纸本)9798331515966

Blockchain technology inherently necessitates redundant computation to achieve consensus among untrusted parties because of its fundamental threat model. this requirement, however, compromises system performance and impedes the widespread adoption of blockchain. To leverage existing physical resources, current research on high-performance consortium blockchain algorithms and architectures frequently employs cluster-node architectures to expand the parallel processing capability of traditional single physical nodes. Our investigation reveals a significant trend as the parallel capability of individual nodes improves. the idle time caused by synchronization of all transactions within each block, previously considered negligible, has become increasingly significant. To address this, we present BachLedger, which implements Seamless Scheduling to fully utilize inter-block thread idle time, thereby augmenting system resource utilization and achieving overall performance improvements. Our experimental results demonstrate that our algorithm surpasses current state-of-the-art (SOTA) performance levels in high-performance consortium blockchains and effectively resolves the aforementioned synchronization issue. Furthermore, this scheduling algorithm offers enhanced scalability for BachLedger, positioning it as a promising solution for future blockchain implementations. © 2024 IEEE.

关键词： Scheduling algorithms

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Innovative Traffic Optimization Techniques: Integrating Braess' Paradox and Vision Transformer architectures (ViT) for Novel Roadway Modalities 7

Innovative Traffic Optimization Techniques: Integrating Brae...

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7th international conference on Natural Language processing and Information Retrieval (NLPIR)

作者： Singh, Siddhant thanikella, Archit Mem High Sch Houston TX 77024 USA Panther Creek High Sch Cary NC USA

ISBN: (纸本)9798400709227

the Traffic Management System employs Braess' paradox to reduce congestion by altering driving patterns and utilizes the Frank-Wolfe method to create efficient routes. Integrated with a state-of-the-art pothole detection model, which utilizes Vision Transformer and Transformer architectures, the system dynamically adapts to road conditions. this innovative approach, trained on a Mumbai Hyperloop station dataset, includes a Two-Way Transformer network for precise road condition analysis, enhancing traffic flow and safety. It has achieved a 35% decrease in traffic congestion, 47% faster incident response, and 33% shorter trip durations. the system's integration of advanced technologies paves the way for future autonomous vehicle networks and offers significant benefits for urban transportation and planning, simultaneously addressing the challenges of potholes and congestion.

关键词： Traffic Adjustment Pothole Detection ViT Transformer Networks Smart Transport Systems

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