this research paper aims to enhance the performance of Number theoretic Transform (NTT) operations in cryptographic applications by leveraging the flexibility and parallelprocessing capabilities of Field Programmable...
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ISBN:
(数字)9798350356236
ISBN:
(纸本)9798350356243
this research paper aims to enhance the performance of Number theoretic Transform (NTT) operations in cryptographic applications by leveraging the flexibility and parallelprocessing capabilities of Field Programmable Gate Arrays (FPGAs). NTT, integral to many cryptographic algorithms, often faces real-time performance challenges due to computational demands. By implementing NTT on FPGAs, this approach introduces features such as parallelism, pipelining, and dynamic memory management, significantly improving computational efficiency. the proposed architecture, utilizing 8T SRAM on the AMD Kintex 7 FPGA KC705 Kit, optimizes memory bandwidth and polynomial multiplication, resulting in a robust, high-speed implementation suitable for real-time cryptographic tasks. Simu-lation results demonstrate substantial performance gains, offering a valuable framework for future cryptographic hardware designs.
It is known that the multiplier is widely applied, and to produce the outputs for the next stage, there is a reliance on the previous stage. Due to this, the multiplication process takes time to complete. As the binar...
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ISBN:
(数字)9798331544607
ISBN:
(纸本)9798331544614
It is known that the multiplier is widely applied, and to produce the outputs for the next stage, there is a reliance on the previous stage. Due to this, the multiplication process takes time to complete. As the binary bit counts of the multiplier and multiplicand increase, it takes longer to generate the output. this longer delay can severely impair the overall performance of digital systems, especially in applications requiring high-speed computations. therefore, optimizing the Multiplier for both speed and power efficiency is crucial to enhancing the performance of modern computing architectures. To achieve this optimization, various techniques such as parallelprocessing and reduced gate counts can be employed. Moreover, utilising advanced algorithms and hardware accelerators can enhance the efficiency of these multipliers in challenging computational settings. this will affect the circuit performance. A new technique known as the reordering technique is implemented in this project to enhance the multiplier in terms of speed and efficiency. this method is implemented by separating the high-state bits from the low-state bits using the reordering circuit, and then the separated bits are processed in the usual manner. this helps in the reduction of critical path latency, which benefits by enhancing the circuit's power consumption as less power is being released as heat or another form.
Aiming at the problems of limited computing power of embedded platform, low target detection probability and high false alarm rate in the process of video small target tracking, a parallel PCA-SIFT algorithm based on ...
ISBN:
(纸本)9798400708305
Aiming at the problems of limited computing power of embedded platform, low target detection probability and high false alarm rate in the process of video small target tracking, a parallel PCA-SIFT algorithm based on Raspberry Pi 4B microprocessor is proposed. the data-level parallel method is used to realize parallel feature extraction and feature point matching, and the computing tasks are assigned to each CPU for parallelprocessing to improve the efficiency of the algorithm. the experimental results show that the algorithm has good adaptability to factors such as target and background clutter, geometric deformation, noise interference and illumination influence, and is close to the serial PCA-SIFT algorithm in image matching effect.
Withthe expansion of modern production line, especially the proposal of the concept of flexible production line, there are more and more production lines in the actual production realization, and more and more signal...
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ISBN:
(数字)9798331510381
ISBN:
(纸本)9798331510398
Withthe expansion of modern production line, especially the proposal of the concept of flexible production line, there are more and more production lines in the actual production realization, and more and more signals need to be controlled, which requires multiple PLCs to be connected in the production line in order to realize the required actual control operation. In this case, the configuration software can not control the production line, so it is necessary to comprehensively schedule and control the whole production line in the computer to realize the real-time control of the production line. Next, taking the German Beckhoff PLC as an example, the TwinCAT3 provided by Beckhoff is used to communicate withthe underlying equipment through the computer. Due to the large number of interfaces that need to be controlled in the flexible production line, this paper adopts the adaptive mode of multi-threaded parallelprocessing to realize the real-time information interaction between the computer operation interface and the underlying equipment.
Text processing, as one of the main issues in the field of artificial intelligence, has received a lot of attention in recent decades. Numerous methods and algorithms are proposed to address the task of semantic textu...
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the data fusion from sensors within the automotive vehicle is vital for improved accuracy and safety. the centralized and information matrix fusion (IMF) algorithms are famous for providing an optimal fusion estimate....
the data fusion from sensors within the automotive vehicle is vital for improved accuracy and safety. the centralized and information matrix fusion (IMF) algorithms are famous for providing an optimal fusion estimate. However, the IMF is not viable in automotive sensor fusion applications due to the limited bandwidth and low hardware resources. Hence, distributed fusion technology is widely adopted in the automotive sensor applications to achieve high-speed and low-area realizations. this paper proposes three digital signal processing (DSP) architectures for covariance intersection (CI) fusion algorithm: Pipelined-traditional CI, adder-ladder CI, and pipelined adder-ladder CI. the proposed DSP architectures are evaluated with hardware resource consumption (multipliers, adders, and delays), maximum achievable frequency, and latency of the architecture. In addition, proposed CI algorithms for Digital Signal processing (DSP) architectures are compared with IMF DSP architectures. the hardware resources and optimal pipeline stages required for CI with respect to N number of sensors are provided. the traditional pipeline algorithm requires N number of stages where as the proposed pipelined version of adder-ladder CI requires a N−1 pipeline stage with additional 7N−1 and 7N−3 delay elements for even and odd number of sensors to achieve the overall system operating frequency to an operation of multiplier. the proposed DSP architectures are suitable for automotive sensor fusion due to their high operating frequency and low hardware resources.
One of the prime research areas today is video summarisation, where the short summary of the input video is generated. the output video content is based on the object of interest. It also saves the time of the viewer;...
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ISBN:
(数字)9798331528348
ISBN:
(纸本)9798331528355
One of the prime research areas today is video summarisation, where the short summary of the input video is generated. the output video content is based on the object of interest. It also saves the time of the viewer; they won't need to view the entire long duration video. To do this process faster, the redundant or steady frames need to be removed first. Background subtraction is one of the techniques used to identify moving objects by calculating the difference between previous and current frame. In our research paper, we have used KNN, MOG2 and CNT for the BGS methods. We have also used different YOLO model like YOLOv3, YOLOv5, YOLOv7 and YOLOv8 to generate annotations file and use them for measuring the performance of the BS algorithms. these methods are implemented using parallelprocessing approach to process more than one video at a time. the performance analysis of these methods is done based on the time of execution and precision. the experiment result shows that the KNN with YOLOv7 perform better and parallelprocessing approach speedup the execution.
Modern vessels possess intricate structures and operate in harsh environments. the safety of their machinery and equipment presents a significant hazard. this paper proposes a fault identification method based on the ...
Modern vessels possess intricate structures and operate in harsh environments. the safety of their machinery and equipment presents a significant hazard. this paper proposes a fault identification method based on the fusion of features and models. Initially, the audio of ship mechanical equipment is processed to extract and fuse identification features, followed by training using an ensemble method of multiple neural network models. Ultimately, by analyzing the training loss and accuracy under various data samples and network models, the optimal data processing and network model fusion methods are established. Experimental results demonstrate that the classification accuracy of this method can reach 91%.
Arrays can improve the performance of inertial sensors, but the lack of synchronization in acquisition times among sensors is a significant challenge. To address this issue, a data acquisition system has been develope...
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ISBN:
(数字)9798350384437
ISBN:
(纸本)9798350384444
Arrays can improve the performance of inertial sensors, but the lack of synchronization in acquisition times among sensors is a significant challenge. To address this issue, a data acquisition system has been developed that uses parallel I2C and SPI buses to enhance measurement precision. this study compares the impact of serial and parallel bus architectures and sensor quantity on the efficacy of inertial sensor arrays. the performance indices used for evaluation include zero bias, zero bias stability, and Allan variance. the experiment indicates that the parallel bus significantly enhances the zero bias stability of the sensors. the incorporation of additional sensors reduces stochastic errors, such as angle random walk, quantization noise, and zero bias. the use of a parallel bus configuration enables easy expansion of the sensor count within the array, thereby significantly enhancing the applicative merit of the inertial sensor array.
Nowadays, Generative Artificial Intelligence (GenAI) is increasingly making inroads in Data Centers, helping to improve aspects related to latency and high speed. Data center-level network infrastructures require mana...
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ISBN:
(数字)9798331532970
ISBN:
(纸本)9798331532987
Nowadays, Generative Artificial Intelligence (GenAI) is increasingly making inroads in Data Centers, helping to improve aspects related to latency and high speed. Data center-level network infrastructures require managing large volumes of data using high-speed protocols such as InfiniBand, as it allows low latency and parallelprocessing, as well as various applied switches at different network architecture levels. In this article, we examine those protocols at the data communication level that GenAI uses to optimize and guarantee data flow between nodes, as well as the design and reference of network architectures in the field of GenIA. On the other hand, the components of the GenAI networks used are analyzed. Similarly, a case study is proposed where the performance of the Graphic processing Units (GPUs) is analyzed based on the definition of a series of metrics such as memory access, memory bandwidth, throughput, energy consumption, temperature, and clock speed, and that through the simulation of neural networks specifically using the Radial Basic Function (RBF) and Multilayer Perceptron (MLP) algorithms, it helps to understand and analyze to what extent these metrics behave and generate possible solutions in the field of data centers.
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